BEOL wiring structures that include an on-chip inductor and an on-chip capacitor, and design structures for a radiofrequency integrated circuit
View Patent ↗Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.
1. A structure comprising:
a substrate including an integrated circuit comprised of a plurality of active devices;
at least one first metallization level including a first dielectric layer and a plurality of first conductive features in the first dielectric layer;
at least one second metallization level including a second dielectric layer and a plurality of second conductive features in the second dielectric layer, the at least one second metallization level disposed vertically between the at least one first metallization level and the substrate;
an on-chip inductor included in the first conductive features of the at least one first metallization level; and
an on-chip capacitor included in the second conductive features of the at least one second metallization level, the on-chip capacitor positioned laterally within the at least one second metallization level such that the on-chip capacitor is in a substantially vertical alignment with the on-chip inductor in the at least one first metallization level, the first dielectric layer is vertically between the first conductive features of the on-chip inductor and the second conductive features of the on-chip inductor, and the second dielectric layer is vertically between the second conductive features of the on-chip capacitor and the substrate.
2. The structure of claim 1 wherein the first and second conductive features electrically connect the on-chip inductor with the on-chip capacitor.
3. The structure of claim 2 wherein the second conductive features of the on-chip capacitor include first and second ports, a plurality of first electrodes directly connected to the first port, and a plurality of second electrodes directly connected to the second port, the first electrodes interleaved with the second electrodes to define an alternating parallel arrangement, and further comprising:
a floating electrode included among the second conductive features in the at least one second metallization level, the floating electrode electrically isolated from the first and second ports and electrically isolated from the first and second electrodes.
4. The structure of claim 3 further comprising:
a switching device configured to connect the floating electrode indirectly with either the first port or the second port.
5. The structure of claim 4 wherein the switching device is one or more field effect transistors of the active devices of the integrated circuit.
6. The structure of claim 1 wherein the at least one first metallization level and the at least one second metallization level are each formed by a damascene process.
7. The structure of claim 1 further comprising:
a third metallization level between the at least one second metallization level and the substrate; and
a Faraday shield positioned laterally in the third metallization level such that the Faraday shield has the substantially vertical alignment with the on-chip inductor and the on-chip capacitor.
8. The structure of claim 1 further comprising:
a third metallization level between the at least one first metallization level and the at least one second metallization level; and
a Faraday shield positioned laterally in the third metallization level such that the Faraday shield also has the substantially vertical alignment with the on-chip inductor and the on-chip capacitor.
9. The structure of claim 1 wherein the second conductive features of the on-chip capacitor are configured to operate as a Faraday shield for the on-chip inductor, and further comprising:
a third metallization level between the at least one first metallization level and the substrate, the third metallization layer being free of a Faraday shield positioned laterally within the third metallization level in the substantially vertical alignment with the on-chip inductor and the on-chip-inductor.
10. The structure of claim 1 further comprising:
a floating conductive feature disposed in the at least one first metallization level, the floating conductive feature electrically isolated from the on-chip capacitor; and
a switching device configured to connect the floating conductive feature indirectly with the on-chip capacitor.
11. The structure of claim 10 wherein the switching device is one or more field effect transistors of the active devices of the integrated circuit.
12. The structure of claim 1 wherein the first and second conductive features are connected with one or more of the active devices of the integrated circuit.
13. The structure of claim 1 wherein the at least one first metallization level includes a third dielectric layer stacked with the first dielectric layer, and the first conductive features of the on-chip inductor are a plurality of signal lines, a first number of the signal lines is included in the first dielectric layer, and a second number of the signal lines is included in the third dielectric layer, and further comprising:
a plurality of vias that connect the signal lines in the first dielectric layer with the signal lines in the third dielectric layer.
14. The structure of claim 1 wherein the at least one second metallization level includes a third dielectric layer stacked with the first dielectric layer, and the second conductive features of the on-chip capacitor are a plurality of electrodes, a first number of the electrodes is included in the first dielectric layer, and a second number of the electrodes is included in the third dielectric layer, and further comprising:
a plurality of vias that connect the electrodes in the first dielectric layer with the electrodes in the third dielectric layer.
15. The structure of claim 1 wherein the integrated circuit is a radiofrequency integrated circuit (RFIC).
16. A back-end-of-line (BEOL) wiring structure fabricated on a substrate carrying an integrated circuit, the BEOL wiring structure comprising:
at least one first metallization level;
at least one second metallization level vertically between the at least one first metallization level and the substrate;
an on-chip inductor including a plurality of signal lines included in the at least one first metallization level;
an on-chip capacitor including a plurality of electrodes included in the at least one second metallization level;
a plurality of conductive features in the at least one first metallization level and the at least one second metallization level, the plurality of conductive features connecting the signal lines of the on-chip inductor with the electrodes of the on-chip capacitor to define an LC resonator having a resonance frequency;
at least one floating electrode included in the at least one second metallization level that is electrically isolated from the electrodes of the on-chip capacitor; and
a switching device configured to connect the at least one floating electrode indirectly with the electrodes of the on-chip capacitor to permit tuning of the resonance frequency of the LC resonator during operation of the integrated circuit.
17. The BEOL wiring structure of claim 16 wherein the on-chip capacitor is positioned laterally within the at least one second metallization level such that the on-chip capacitor is in a substantially vertical alignment with the on-chip inductor in the at least one first metallization level.
18. The BEOL wiring structure of claim 17 further comprising:
a third metallization between the at least one first metallization level and the at least one second metallization level; and
a Faraday shield positioned laterally within the third metallization level such that the Faraday shield has the substantially vertical alignment with the on-chip inductor and the on-chip capacitor.
19. The BEOL wiring structure of claim 17 further comprising:
a third metallization between the substrate and the at least one second metallization level; and
a Faraday shield positioned laterally within the third metallization level such that the Faraday shield has the substantially vertical alignment with the on-chip inductor and the on-chip capacitor.
20. The BEOL wiring structure of claim 17 wherein the electrodes of the on-chip capacitor are configured to operate as a Faraday shield for the on-chip inductor, and further comprising:
a third metallization level between the at least one first metallization level and the substrate, the third metallization layer being free of a Faraday shield positioned laterally within the third metallization level in the substantially vertical alignment with the on-chip inductor and the on-chip capacitor.
21. The BEOL wiring structure of claim 16 wherein the integrated circuit is a radiofrequency integrated circuit (RFIC).
22. The BEOL wiring structure of claim 16 wherein the at least one first metallization level and the at least one second metallization level are each formed by a damascene process.
23. The BEOL wiring structure of claim 16 wherein the switching device is one or more field effect transistors of the active devices of the integrated circuit.
24. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
at least one first metallization level including a first dielectric layer and a plurality of first conductive features in the first dielectric layer;
at least one second metallization level including a second dielectric layer and a plurality of second conductive features in the second dielectric layer, the at least one second metallization level disposed vertically between the at least one first metallization level and a substrate;
an on-chip inductor included in the first conductive features of the at least one first metallization level; and
an on-chip capacitor included in the second conductive features of the at least one second metallization level, the on-chip capacitor positioned laterally within the at least one second metallization level such that the on-chip capacitor is in a substantially vertical alignment with the on-chip inductor in the at least one first metallization level with at least a portion of the first dielectric layer or at least a portion of the second dielectric layer vertically between the first conductive features of the on-chip inductor and the second conductive features of the on-chip capacitor, the first dielectric layer is vertically between the first conductive features of the on-chip inductor and the second conductive features of the on-chip inductor, and the second dielectric layer is vertically between the second conductive features of the on-chip capacitor and the substrate.
25. The design structure of claim 24 wherein the design structure comprises a netlist.
26. The design structure of claim 24 wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
27. The design structure of claim 24 wherein the design structure resides in a programmable gate array.