IP Library Granted Patent US 8,129,266
Granted Patent B2
US 8,129,266 · App. 12/170,202 · Granted Mar 6, 2012

Method of forming a shielded semiconductor device and structure therefor

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Quick Facts
Patent No.
US 8,129,266
App. No.
12/170,202
Granted
Mar 6, 2012
Kind
B2
Abstract

In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.

Claims (26)

1. A method of forming a shielded semiconductor device comprising:

providing a semiconductor substrate;

forming active semiconductor devices on a surface of the semiconductor substrate;

forming a plurality of conductor layers overlying at least a portion of the active semiconductor devices wherein the plurality of conductor layers interconnect at least a portion of the active semiconductor devices and wherein at least one inter-layer dielectric is interposed between the portion of the active semiconductor devices and the plurality of conductor layers wherein the inter-layer dielectric overlies the surface of the semiconductor substrate;

forming a metal shield layer overlying the plurality of conductor layers;

forming a passivation layer used to protect the shielded semiconductor device from contaminants overlying the inter-layer dielectric and underlying the metal shield layer wherein the metal shield layer is separated from the plurality of conductor layers by the passivation layer and wherein the metal shield layer is not coupled to electrical signals or electrical potentials distributed among the active semiconductor.

2. The method of claim 1 wherein forming the passivation layer includes forming the passivation layer with a thickness that is greater than a thickness of the inter-layer dielectric.

3. The method of claim 2 further including forming a second dielectric layer overlying the metal shield layer; and

forming a conductor re-distribution layer on the second dielectric layer.

4. The method of claim 1 wherein forming the metal shield layer includes forming the passivation layer with a thickness of about two to fifteen microns.

5. The method of claim 1 wherein forming the passivation layer includes forming the passivation layer to include silicon nitride.

6. The method of claim 1 wherein forming the plurality of conductor layers includes forming each conductor layer of the plurality of conductor layers to have a conductor having a width, and

wherein forming the metal shield layer includes forming a metal on the surface of the passivation layer and patterning the metal to form a plurality of metal regions that have a width that is greater than the width of the conductor of the plurality of conductor layers.

7. The method of claim 1 further including forming the metal shield layer from copper.

8. A method of forming a semiconductor device comprising:

forming the semiconductor device to include a plurality of conductor layers that interconnect electrical signals between active regions of semiconductor elements of the semiconductor device wherein at least a portion of the plurality of conductor layers overlie at least a portion of the active regions and are separated from the active regions by at least one inter-layer dielectric that is formed with a first thickness;

forming a metal shield layer overlying the plurality of conductor layers wherein the metal shield layer is separated from the plurality of conductor layers by a passivation layer used to protect the semiconductor device from contaminants overlying the plurality of interconnect layers and underlying the metal shield layer and wherein the metal shield layer does not distribute electrical signals or electrical potentials to the active regions including forming the metal shield layer with a thickness that is greater than the first thickness of the inter-layer dielectric; and

forming a second dielectric layer overlying the metal shield layer.

9. The method of claim 8 wherein forming the passivation layer includes forming the passivation layer to include a layer of silicon nitride.

10. The method of claim 8 further including forming a signal re-distribution layer overlying the metal shield layer.

11. A method of forming a semiconductor device comprising:

forming the semiconductor device to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device wherein the plurality of conductor layers are separated by at least one inter-layer dielectric that is formed with a first thickness;

forming a metal shield layer overlying the plurality of conductor layers wherein the metal shield layer is separated from the plurality of conductor layers by a first dielectric layer including forming the metal shield layer with a thickness that is greater than the first thickness of the inter-layer dielectric;

forming a second dielectric layer overlying the metal shield layer;

forming an antenna on the second dielectric layer; and

forming a coaxial connector base on the second dielectric layer wherein a material of the antenna is different from a material of the coaxial connector base.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →