IP Library Granted Patent US 7,842,969
Granted Patent B2
US 7,842,969 · App. 12/170,630 · Granted Nov 30, 2010

Low clamp voltage ESD device and method therefor

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Quick Facts
Patent No.
US 7,842,969
App. No.
12/170,630
Granted
Nov 30, 2010
Kind
B2
Abstract

In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.

Claims (18)

1. A low clamp voltage ESD device comprising:

a semiconductor substrate of a first conductivity type having a first doping concentration, the semiconductor substrate having first and second surfaces;

a first semiconductor layer of a second conductivity type on the first surface of the semiconductor substrate, the first semiconductor layer having a second doping concentration and having a first surface that is opposite to the first surface of the semiconductor substrate;

a first semiconductor region of the second conductivity type positioned between a first portion of the first semiconductor layer and the first surface of the semiconductor substrate, the first semiconductor region having a first thickness and a third doping concentration that is greater than the second doping concentration wherein the first semiconductor region forms a zener diode with dopants of the semiconductor substrate;

a second semiconductor region of the first conductivity type and a fourth doping concentration that is greater than the second doping concentration formed on the first surface of the first semiconductor layer and overlying a first portion of the first semiconductor region wherein the second semiconductor region forms a first P-N diode with the first semiconductor layer; and

a first conductor extending from the first surface of the first semiconductor layer through the first semiconductor layer and intersecting the first semiconductor region, the first conductor adjacent to and spaced a first distance from the second semiconductor region wherein the first distance is no greater than the first thickness of the first semiconductor region wherein the first conductor forms a conduction path for current to flow from the first P-N diode to the zener diode.

2. The ESD device of claim 1 wherein the ESD device is devoid of a doped region of the first conductivity type positioned between the first P-N diode and the first semiconductor region.

3. The ESD device of claim 1 wherein the first doping concentration is no less than approximately 1×10 19 atoms/cm 3 and the second doping concentration is no greater than approximately 1×10 17 atoms/cm 3 .

4. The ESD device of claim 1 wherein the first conductor includes a plurality of conductors of the second conductivity type having a doping concentration that is greater than the second doping concentration, the plurality of conductors having a proximate end adjacent to and spaced the first distance from the second semiconductor region, a portion of the plurality of conductors extending laterally away from the second semiconductor region.

5. The ESD device of claim 1 further including a first blocking structure formed as a first closed polygon having a periphery that surrounds a periphery of the second semiconductor region and the first conductor, the first blocking structure extending from the first surface of the first semiconductor layer through the first semiconductor region; and

a third semiconductor region of the first conductivity type formed in the first semiconductor layer and external to the first closed polygon, the third semiconductor region forming a second P-N diode.

6. The ESD device of claim 5 further including a fourth semiconductor region of the second conductivity type within the first closed polygon and overlying a third portion of the first semiconductor region, wherein the fourth semiconductor region forms a second P-N diode, the fourth semiconductor region spaced laterally apart from both the first conductor and the second semiconductor region; and

a second conductor extending from the first surface of the first semiconductor layer through the first semiconductor layer and intersecting the first semiconductor region, the second conductor adjacent to and spaced the first distance from the fourth semiconductor region wherein the second conductor forms a conduction path for current to flow from the second P-N diode to the zener diode.

7. The ESD device of claim 6 wherein the first blocking structure includes a third conductor of the second conductivity type having a doping concentration that is greater than the second doping concentration, the third conductor extending from the first surface of the first semiconductor layer through the first semiconductor layer to the first semiconductor region wherein the third conductor surrounds the first P-N diode and the first.conductor.

8. The ESD device of claim 1 further including a first doped region of the second conductivity type formed on a surface of the first semiconductor layer and overlying a second portion of the first semiconductor region, the first doped region laterally separated from the second semiconductor region wherein the first conductor is positioned between the first doped region and the second semiconductor region.

9. The ESD device of claim 8 further including a second conductor forming electrical contact to the first doped region at the surface of the first semiconductor layer.

10. The ESD device of claim 1 further including a second P-N diode formed as a doped region of the first conductivity type overlying a second portion of the first semiconductor region and spaced laterally apart from the second semiconductor region and from the first conductor.

11. The ESD device of claim 1 wherein the first conductor includes a lattice work of interconnected conductors that all extend from the first surface of the first semiconductor layer through the first semiconductor layer and intersect the first semiconductor region wherein at least a portion of the lattice work of interconnected conductors form the conduction path for current to flow from the first P-N diode to the zener diode.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2008
From: MARREIRO, DAVID D.; SHASTRI, SUDHAMA C.; SALIH, ALI; LIU, MINGJIAO; PARSEY, JOHN MICHAEL, JR.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C.
Reel/Frame 021219/0744 →