Deglitching circuits for a radiation-hardened static random access memory based programmable architecture
View Patent ↗A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.
1. A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising:
providing a configuration memory having a plurality of configuration bits;
coupling read and write circuitry to said configuration memory for configuring said plurality of configuration bits, wherein said configuration memory comprises a plurality of inverters, the output of a first inverter of said plurality of inverters is coupled to the input of a second inverter of said plurality of inverters, and the input of said first inverter is coupled to the output of said second inverter of said plurality of inverters;
coupling a radiation hard latch to a programmable element, said radiation hard latch controlling said programmable element; and
providing an interface that couples at least one of said plurality of configuration bits to said radiation hard latch when said write circuitry writes to said at least one of said plurality of configuration bits.
2. The method of claim 1 , wherein:
said radiation hard latch comprises a plurality of inverters, the output of a first of said plurality of inverters is coupled to the input of a second inverter of said plurality of inverters and the input of said first inverter is coupled to the output of said second inverter of said plurality of inverters.
3. The method of claim 2 , wherein:
said plurality of inverters of said radiation hard latch each comprises a pair of MOS transistors.
4. The method of claim 3 , wherein:
the P-channel drive strength of said pair of MOS transistors is approximately double the N-channel drive strength of said pair of MOS transistors.
5. The method of claim 3 , wherein:
the P-channel width-to-length (W/L) ratio of said pair of MOS transistors is about approximately 30/0.24 micrometers.
6. The method of claim 3 , wherein:
the N-channel width-to-length (W/L) ratio of said pair of MOS transistors is about approximately 15/0.24 micrometers.
7. The method of claim 1 , wherein:
said interface comprises a plurality of sets of gates.
8. The method of claim 7 , wherein:
said sets of gates comprise pass transistors.
9. The method of claim 1 , wherein:
each of said plurality of configuration bits comprises a non-inverted output connected to said radiation hard latch through a control gate.
10. The method of claim 1 , wherein:
each of said plurality of configuration bits comprises an inverted output connected to said radiation hard latch through a control gate.
11. The method of claim 1 , wherein:
said radiation hard latch further comprises an inverted output and a non-inverted output.
12. The method of claim 1 , further comprising:
providing a second radiation hard latch coupled to said radiation hard latch.
13. The method of claim 12 , wherein:
said second radiation hard latch is coupled to said radiation hard latch through a plurality of NAND stacks.
14. The method of claim 12 , wherein:
said second radiation hard latch comprises two cross-coupled inverters.