IP Library Granted Patent US 9,293,385
Granted Patent B2
US 9,293,385 · App. 12/182,132 · Granted Mar 22, 2016

RDL patterning with package on package system

Inventors: Reza Argenty Pagaila (Singapore, SG); Byung Tai Do (Singapore, SG); Dioscoro A. Merilo (Singapore, SG)
Assignee: STATS ChipPAC Ltd.
H01L23/3128H01L21/561H01L24/97H01L25/105H01L23/49548H01L23/49816H01L23/5389H01L24/48H01L2224/16H01L2224/16225H01L2224/32145H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73253H01L2224/73265H01L2224/8592H01L2224/97H01L2225/1023H01L2225/1041H01L2225/1058H01L2225/1088H01L2924/01027H01L2924/01033H01L2924/14H01L2924/15331H01L2924/15787H01L2924/181H01L2924/1815
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,293,385
App. No.
12/182,132
Granted
Mar 22, 2016
Kind
B2
Abstract

An integrated circuit package system includes: providing an internal device; encapsulating the internal device with an encapsulation having an outer surface; and forming a redistribution line having connection points on the outer surface of the encapsulation.

Claims (40)

1. A method of manufacture of an integrated circuit package system comprising:

providing a substrate;

providing an internal device on and above the substrate;

encapsulating the internal device with an encapsulation having an outer surface;

forming a redistribution line, directly on the outer surface, the redistribution line having:

a central portion in direct contact with the internal device, the central portion completely within the width of the internal device and not extending beyond edges thereof,

peripheral portions around the central portion, the peripheral portions extending above the internal device and beyond the edges thereof such that sections of the peripheral portions are above the substrate,

interior portions between the central portion and the peripheral portions, the interior portions tapering from the peripheral portions to the central portion, the interior portions completely within the width of the internal device and not extending beyond the edges thereof,

exterior portions in contact with the peripheral portions opposite the interior portions, the exterior portions tapering from the peripheral portions to make direct contact with the substrate;

forming an inner array and outer array of connection points, the inner array etched on the central portion and bordered on at least two opposing sides by the outer array, the outer array etched on the peripheral portion and elevated a standoff height higher than the inner array to form two levels of the connection points, the inner array and the outer array exposed from the encapsulation, the connection points connected by the redistribution line for conducting electrical signals between the connection points, the connection points and the redistribution line formed of the same material;

mounting a first external device above the inner array on the central portion of the redistribution line, the first external device above the substrate, above portions of the encapsulation, and above the internal device, wherein an upper surface of the first external device is at a higher vertical elevation than the peripheral portions, the interior portions, and the exterior portions of the redistribution line; and

connecting the first external device to the redistribution line with an interconnect below the first external device, the interconnect in direct contact with the central portion of the redistribution line, the interconnect being above the substrate, above portions of the encapsulation, and above the internal device, the interconnect and the interior portions being at substantially similar horizontal axis.

2. The method as claimed in claim 1 further comprising:

depositing an insulator between the connection points on the redistribution line.

3. The method as claimed in claim 1 wherein:

encapsulating the internal device with the encapsulation includes encapsulating with the encapsulation having a mold riser providing the standoff height.

4. The method as claimed in claim 1 further comprising:

forming the redistribution line on an exposed surface of the internal device.

5. The method as claimed in claim 1 further comprising:

mounting an under-fill between the first external device and the redistribution line.

6. An integrated circuit package system comprising:

a substrate;

an internal device on and above the substrate;

an encapsulation having an outer surface encapsulating the internal device;

a redistribution line, formed directly on the outer surface, the redistribution line having:

a central portion in direct contact with the internal device, the central portion completely within the width of the internal device and not extending beyond edges thereof,

peripheral portions around the central portion, the peripheral portions extending above the internal device and beyond the edges thereof such that sections of the peripheral portions are above the substrate,

interior portions between the central portion and the peripheral portions, the interior portions tapering from the peripheral portions to the central portion, the interior portions completely within the width of the internal device and not extending beyond the edges thereof,

exterior portions in contact with the peripheral portions opposite the interior portions, the exterior portions tapering from the peripheral portions to make direct contact with the substrate;

an inner array and an outer array of connection points, the inner array etched on the central portion and bordered on at least two opposing sides by the outer array, the outer array etched on the peripheral portion and elevated a standoff height higher than the inner array to form two levels of the connection points, the inner array and the outer array exposed from the encapsulation, the connection points connected by the redistribution line for conducting electrical signals between the connection points, the connection points and the redistribution line formed of the same material;

a first external device mounted above the inner array on the central portion of the redistribution line, the first external device above the substrate, above portions of the encapsulation, and above the internal device, wherein an upper surface of the first external device is at a higher vertical elevation than the peripheral portions, the interior portions, and the exterior portions of the redistribution line; and

an interconnect below the first external device for connecting the first external device to the redistribution line, the interconnect in direct contact with the central portion of the redistribution line, the interconnect being above the substrate, above portions of the encapsulation, and above the internal device, the interconnect and the interior portions being at substantially similar horizontal axis.

7. The system as claimed in claim 6 further comprising:

an insulator deposited between the connection points on the redistribution line.

8. The system as claimed in claim 6 wherein:

the encapsulation has a mold riser providing the standoff height.

9. The system as claimed in claim 6 further comprising:

an exposed surface of the internal device and having the redistribution line formed thereover.

10. The system as claimed in claim 6 further comprising:

an under-fill mounted between the first external device and the redistribution line.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 11, 2008
From: PAGAILA, REZA ARGENTY; DO, BYUNG TAI; MERILO, DIOSCORO A.
To: STATS CHIPPAC LTD.
Reel/Frame 021368/0006 →
Continuity (1)
Related Publication 20100025833A1 · Feb 4, 2010