IP Library Granted Patent US 8,102,666
Granted Patent B2
US 8,102,666 · App. 12/194,506 · Granted Jan 24, 2012

Integrated circuit package system

Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,102,666
App. No.
12/194,506
Granted
Jan 24, 2012
Kind
B2
Abstract

An integrated circuit package system includes: connecting a carrier and an integrated circuit mounted thereover; mounting an interposer, having an opening, over the integrated circuit; connecting an interconnect between the interposer and the carrier through the opening; and forming an encapsulation planar with a carrier vertical side of the carrier and an interposer vertical side of the interposer.

Claims (15)

1. An integrated circuit package system comprising:

a carrier;

an integrated circuit over the carrier;

an interposer, having an opening, over the integrated circuit;

an interconnect between the interposer having the opening and the carrier through the opening; and

an encapsulation planar with a carrier vertical side of the carrier and an interposer vertical side of the interposer.

2. The system as claimed in claim 1 wherein the interposer includes a contact pad exposed from the encapsulation.

3. The system as claimed in claim 1 wherein the encapsulation includes an encapsulation protrusion above the opening of the interposer.

4. The system as claimed in claim 1 further comprising a thermal structure over the interposer.

5. The system as claimed in claim 1 further comprising a device over the interposer.

6. The system as claimed in claim 1 further comprising a spacer between the integrated circuit and the interposer.

7. The system as claimed in claim 6 wherein the encapsulation includes an encapsulation protrusion through the opening and over the interconnect.

8. The system as claimed in claim 6 wherein the integrated circuit includes a stack of integrated circuits.

9. The system as claimed in claim 6 wherein the spacer includes a wire-in-film B-stage penetrable material.

10. The system as claimed in claim 6 wherein the spacer is over a portion of a first interconnect adjacent to a connection with the integrated circuit.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
RELEASE OF SECURITY INTEREST Recorded Jun 9, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052879/0852 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2008
From: PARK, HYUNGSANG; YOON, IN SANG; YANG, DEOKKYUNG; PARK, SOO-SAN
To: STATS CHIPPAC LTD.
Reel/Frame 021459/0019 →
Continuity (1)
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