Current limited voltage supply
View Patent ↗A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit.
1. An integrated circuit comprising:
a plurality of digital logic cells that undergo logic transitions during normal operation of the integrated circuit;
a supply line coupled to the digital logic cells, wherein the supply line provides a supply current to the digital logic cells during normal operation of the integrated circuit;
a current limited voltage supply comprising a first transistor coupled between a first voltage supply terminal and the supply line, and a capacitor coupled to the supply line, wherein the capacitor supplies a discharging current to the supply line while the digital logic cells undergo logic transitions; and
a bias circuit coupled to the first transistor in a current mirror configuration, whereby a constant reference current within the bias circuit is mirrored to the first transistor.
2. The integrated circuit of claim 1 , wherein the capacitor receives a charging current from the first transistor during periods while the digital logic cells do not undergo logic transitions.
3. The integrated circuit of claim 1 , wherein the first transistor is a P-channel MOS transistor, and the first voltage supply terminal provides a positive supply voltage.
4. The integrated circuit of claim 1 , wherein the capacitor is further coupled to a second voltage supply terminal.
5. The integrated circuit of claim 4 , wherein the second voltage supply terminal is a ground supply terminal.
6. The integrated circuit of claim 1 further comprising:
an analog circuit; and
a second transistor coupled between the first voltage supply terminal and the analog circuit, wherein the bias circuit is coupled to the second transistor in a current mirror configuration, whereby the constant reference current within the bias circuit is mirrored to the second transistor, such that an analog supply current flows through the second transistor to the analog circuit.
7. The integrated circuit of claim 1 , wherein the plurality of digital logic cells exhibit an increase in switching current of I D (Amps) for a duration of T (seconds) during the logic transitions, wherein the supply line has a desired voltage fluctuation of V (Volts) during normal operation of the integrated circuit, and wherein the capacitor is sized to have a capacitance of (I D ×T)/V.
8. An integrated circuit comprising:
a constant current source that provides a reference current;
a current mirror circuit coupled to the constant current source, wherein the current mirror circuit mirrors the reference current to a first transistor, such that a source current flows through the first transistor;
a plurality of digital logic cells coupled between a drain of the first transistor and a ground supply terminal; and
a capacitor coupled between the drain of the first transistor and the ground supply terminal.
9. The integrated circuit of claim 8 , wherein the digital logic cells undergo logic transitions during normal operation of the integrated circuit, wherein the capacitor is charged from the source current when the digital logic cells are not undergoing logic transitions, and wherein the capacitor is discharged through the digital logic cells while the digital logic cells are undergoing logic transitions.
10. The integrated circuit of claim 8 , further comprising an analog circuit, wherein the current mirror circuit further mirrors the reference current to a second transistor, such that an analog supply current flows through the second transistor, wherein the analog supply current is provided to the analog circuit.
11. The integrated circuit of claim 8 , wherein the digital logic cells undergo logic transitions during normal operation of the integrated circuit, wherein the plurality of digital logic cells exhibit an increase in switching current of I D (Amps) for a duration of T (seconds) during the logic transitions, wherein the supply line has a desired voltage fluctuation of V (Volts) during normal operation of the integrated circuit, and wherein the capacitor is sized to have a capacitance of (I D ×T)/V.
12. A method of operating an integrated circuit comprising:
generating a first supply current by mirroring a constant reference current through a first transistor;
powering digital logic cells of the integrated circuit from the first supply current, wherein the digital logic cells undergo logic transitions during normal operation of the integrated circuit;
charging a capacitor from the first supply current during a first period, wherein the digital logic cells are not undergoing logic transitions during the first period; and
discharging the capacitor to the digital logic cells during a second period, wherein the digital logic cells are undergoing logic transitions during the second period.
13. The method of claim 12 , further comprising:
generating a second supply current by mirroring the constant reference current through a second transistor; and
powering analog circuitry of the integrated circuit from the second supply current.