IP Library Granted Patent US 8,823,160
Granted Patent B2
US 8,823,160 · App. 12/197,209 · Granted Sep 2, 2014

Integrated circuit package system having cavity

Inventors: Jong-Woo Ha (Seoul, KR); DaeSik Choi (Seoul, KR); DeokKyung Yang (Hanam-si, KR)
Assignee: STATS ChipPAC Ltd.
H01L23/49811H01L2924/15311H01L2224/48227H01L2224/32225H01L2224/48091H01L24/48H01L2225/06568H01L2225/1088H01L2924/3511H01L2924/15331H01L2224/32145H01L23/3128H01L2224/73265H01L25/105H01L2225/1058H01L2225/1023H01L2224/48225
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Quick Facts
Patent No.
US 8,823,160
App. No.
12/197,209
Granted
Sep 2, 2014
Kind
B2
Abstract

An integrated circuit package system includes providing a carrier having a first side and a second side; mounting an integrated circuit over the carrier with the first side facing the integrated circuit; attaching an external interconnect to the second side; and forming an encapsulation over the integrated circuit and around the external interconnect with the external interconnect exposed from the encapsulation and with the encapsulation and the second side forming a cavity.

Claims (44)

1. A method of manufacturing an integrated circuit package system comprising:

providing a carrier having a first side and a second side;

mounting an integrated circuit over the carrier with the first side facing the integrated circuit;

attaching an external interconnect to the second side;

forming an encapsulation over the integrated circuit and around the external interconnect with the encapsulation and the second side forming a cavity, the external interconnect exposed from the encapsulation and the second side exposed in the cavity;

providing a mountable structure;

attaching an un-encapsulated conductive structure between the external interconnect and the mountable structure, wherein the un-encapsulated conductive structure has a same structure and is made of a same conductive as the external interconnect; and

mounting an encapsulated integrated circuit on the mountable structure such that the encapsulated integrated circuit nests entirely within the cavity.

2. The method as claimed in claim 1 wherein forming the encapsulation includes exposing the external interconnect at a bottom side of the encapsulation.

3. The method as claimed in claim 1 wherein forming the encapsulation includes forming a bottom side facing away from the carrier and planar with the external interconnect.

4. The method as claimed in claim 1 wherein attaching the external interconnect includes attaching the external interconnect with a reduced dimension.

5. The method as claimed in claim 1 wherein forming the encapsulation includes forming the encapsulation having a groove in a bottom of the encapsulation and the external interconnect exposed in the groove.

6. The method as claimed in claim 5 wherein attaching the un-encapsulated conductive structure includes forming the external interconnect within the groove.

7. The method as claimed in claim 5 wherein attaching the un-encapsulated conductive structure includes forming the un-encapsulated conductive structure within the groove.

8. The method system as claimed in claim 1 further comprising mounting an electrical interconnect to the mountable structure.

9. A method of manufacturing an integrated circuit package system comprising:

providing a carrier having a first side and a second side;

mounting an integrated circuit over the carrier with the first side facing the integrated circuit;

attaching an external interconnect to the second side;

forming an encapsulation over the integrated circuit and around the external interconnect including:

forming the encapsulation having a bottom side facing away from the carrier and with the encapsulation and the second side forming a cavity, the second side exposed in the cavity, and

exposing the external interconnect at the bottom side;

providing a mountable structure;

attaching a un-encapsulated solder ball between the external interconnect and the mountable structure; and

mounting an encapsulated integrated circuit on the mountable structure such that the encapsulated integrated circuit nests entirely within the cavity.

10. The method as claimed in claim 9 further comprising:

attaching an electrical interconnect under the mountable structure.

11. The method as claimed in claim 9 wherein attaching the external interconnect includes attaching the external interconnect with a reduced dimension.

12. The method as claimed in claim 9 wherein forming the encapsulation includes forming the encapsulation having a groove in a bottom of the encapsulation and the external interconnect exposed in the groove.

13. The method as claimed in claim 9 further comprising mounting an electrical interconnect to the mountable structure.

14. An integrated circuit package system comprising:

a carrier having both a first side and a second side;

an integrated circuit over the carrier with the first side facing the integrated circuit;

an external interconnect attached to the second side;

an encapsulation over the integrated circuit and around the external interconnect with the encapsulation and the second side forming a cavity, the external interconnect exposed from the encapsulation and the second side exposed in the cavity;

a mountable structure;

an un-encapsulated conductive structure between the external interconnect and the mountable structure, wherein the un-encapsulated conductive structure has a same structure and is made of a same conductive material as the external interconnect; and

an encapsulated integrated circuit over the mountable structure, wherein the encapsulated integrated circuit nests entirely within the cavity, and wherein the external interconnect is over the mountable structure.

15. The system as claimed in claim 14 wherein the external interconnect is exposed at a bottom side of the encapsulation.

16. The system as claimed in claim 14 wherein the encapsulation includes a bottom side facing away from the carrier and planar with the external interconnect.

17. The system as claimed in claim 14 wherein the external interconnect has a reduced dimension.

18. The system as claimed in claim 14 wherein the un-encapsulated conductive structure includes a solder ball.

19. The system as claimed in claim 14 wherein the encapsulation has a groove in a bottom of the encapsulation and the external interconnect exposed in the groove.

20. The system as claimed in claim 19 wherein the un-encapsulated conductive structure is within the groove.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE ASSIGNEE'S NAME ON THE COVER SHEET PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0161. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064805/0735 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0161 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2008
From: HA, JONG-WOO; CHOI, DAESIK; YANG, DEOKKYUNG
To: STATS CHIPPAC LTD.
Reel/Frame 021611/0897 →
Continuity (1)
Related Publication 20100044878A1 · Feb 25, 2010