IP Library Granted Patent US 8,292,690
Granted Patent B2
US 8,292,690 · App. 12/206,043 · Granted Oct 23, 2012

Thinned semiconductor wafer and method of thinning a semiconductor wafer

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Quick Facts
Patent No.
US 8,292,690
App. No.
12/206,043
Granted
Oct 23, 2012
Kind
B2
Abstract

A thinned semiconductor wafer and a method for thinning the semiconductor wafer. A semiconductor wafer is thinned from its backside to form a cavity in a central region of the backside of the semiconductor wafer. Forming the cavity also forms a ring support structure in a peripheral region of the semiconductor wafer. The ring support structure has an inner edge and an outer edge. The inner edge may be beveled or have a stepped shape.

Claims (34)

1. A method for thinning a semiconductor wafer, comprising:

providing the semiconductor wafer having first and second sides and a major surface;

removing a first portion of the semiconductor material by grinding the semiconductor wafer from the second side using a grinding wheel to form a first portion of a cavity having a first depth and a first lateral dimension;

removing a second portion of the semiconductor material by grinding the semiconductor wafer from the second side using the grinding wheel to form a second portion of the cavity having a second depth and a second lateral dimension;

removing a third portion of the semiconductor material by grinding the semiconductor wafer from the second side using the grinding wheel to form a third portion of the cavity having a third depth and a third lateral dimension;

removing a fourth portion of the semiconductor material by grinding the semiconductor wafer from the second side using the grinding wheel to form a fourth portion of the cavity having a fourth depth and a fourth lateral dimension to form a ring support structure in the second side of the semiconductor wafer, wherein the ring support structure has first and second support portions and wherein a width of the second support portion is greater than a width of the first support portion, wherein the first lateral dimension is greater than the second lateral dimension which is greater than the third lateral dimension.

2. The method of claim 1 , wherein removing the first, second, third, and fourth portions of the ring support structure includes forming the ring support structure as a stepped structure.

3. The method of claim 1 , wherein grinding the semiconductor wafer comprises:

grinding from the back side of the semiconductor wafer to form a first step having a first width; and

grinding from the back side of the semiconductor wafer to form a second step having a second width, the second width greater than the first width.

4. The method of claim 3 , wherein grinding the semiconductor wafer comprises grinding the back side of the semiconductor wafer to form a plurality of steps.

5. The method of claim 4 , wherein each step of the plurality of steps has a different width from the other steps of the plurality of steps.

6. The method of claim 3 , further including using the grinding wheel to form the plurality of steps and wherein the width of one or more of the steps of the plurality of steps is greater than the diameter of the grinding wheel.

7. The method of claim 2 , wherein removing the first, second, and third portions of the semiconductor material includes moving the grinding wheel in a direction substantially parallel to the major surface.

8. The method of claim 7 , further including:

laterally moving the grinding wheel a first distance to form a first step of the stepped structure; and

laterally moving the grinding wheel a second distance to form a second step of the stepped structure, the second distance less that the first distance.

9. The method of claim 7 , further including programming the grinder to move the grinding wheel.

10. The method of claim 1 , wherein removing the first, second, and third portions of the semiconductor material further includes spiraling the grinding wheel into the semiconductor wafer.

11. A method for forming a ring support structure from a semiconductor wafer, comprising:

providing the semiconductor wafer having first and second surfaces on first and second sides of the semiconductor wafer, respectively;

removing a plurality of portions of the semiconductor wafer from the second side to form a cavity, wherein removing the plurality of portions comprises:

removing a first portion of the semiconductor wafer from the second side to form a first portion of the cavity, the first portion of the cavity having a first lateral dimension and a first vertical dimension;

removing a second portion of the semiconductor wafer from the second side to form a second portion of the cavity, the second portion of the cavity having a second lateral dimension and a second vertical dimension; and

removing a third portion of the semiconductor wafer from the second side to form a third portion of the cavity, the third portion of the cavity having a third lateral dimension and a third vertical dimension, the second lateral dimension greater than the first lateral dimension, wherein the first vertical dimension and the first lateral dimension in cooperation with the second vertical dimension and the second lateral dimension and the third vertical dimension and the third lateral dimension form a line having a substantially constant slope.

12. The method of claim 11 , wherein removing the first and second portions forms a stepped structure.

13. The method of claim 11 , wherein removing the first and second portions forms a beveled structure.

14. The method of claim 11 , further including using a grinding wheel to remove the plurality of portions.

15. The method of claim 14 , wherein using the grinding wheel includes moving the grinding wheel along the backside of the semiconductor wafer in a direction substantially parallel to the first major surface.

16. The method of claim 15 , further including programming a grinder to move the grinding wheel.

17. A semiconductor wafer having a major surface, first and second edges, and a ring support structure, wherein the ring support structure comprises a rim having at least first, second, third, and fourth portions, wherein the first portion has a first width and a first depth, the second portion has a second width and a second depth, the third portion has a third width and a third depth, and the fourth portion has a fourth width and a fourth depth, the second width greater than the first width, the third width greater than the second width, and the fourth width greater than the third width, and wherein the major surface extends from the first edge to the second edge of the semiconductor wafer.

18. The semiconductor wafer of claim 17 , wherein the rim has a beveled portion that extends from the first portion to the fourth portion.

19. The semiconductor wafer of claim 17 , wherein the rim has a stepped portion.

20. The semiconductor wafer of claim 19 , wherein the ring support structure has first and second edges, and wherein the stepped portion is formed from the first edge.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2008
From: SEDDON, MICHAEL J.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 021494/0045 →