Method of forming an integrated semiconductor device and structure therefor
View Patent ↗In one embodiment, a plurality of ESD devices are used to form an integrated semiconductor filter circuit. Additional diodes are formed in parallel with the ESD structures in order to increase the input capacitance.
1. A method of forming an integrated semiconductor device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first doped region of a second conductivity type on a surface of the semiconductor substrate;
forming a second doped region of the first conductivity type on a surface of the first doped region wherein the second doped region and the first doped region form a first diode;
forming a third doped region of the second conductivity type on the surface of the semiconductor substrate and underlying the second doped region wherein the third doped region and a first portion of the semiconductor substrate form a first zener diode that is coupled in series with the first diode;
forming a fourth doped region of the second conductivity type on the surface of the first doped region and spaced laterally apart from the second doped region wherein an interface between the semiconductor substrate and a first portion of the first doped region that underlies the fourth doped region forms a second diode that is coupled in parallel with the series combination of the first diode and the first zener diode; and
forming a fifth doped region of the second conductivity type on the surface of the semiconductor substrate wherein the fifth doped region and a second portion of the semiconductor substrate form a third diode that is coupled in parallel with the second diode.
2. The method of claim 1 further including forming a sixth doped region of the second conductivity type on the surface of the first doped region, the sixth doped region overlying the fifth doped region and spaced laterally apart from the second and fourth doped regions.
3. The method of claim 1 wherein forming the fifth doped region includes forming the fifth doped region underlying the fourth doped region and positioned so that the second portion of the semiconductor substrate underlies the fifth doped region.
4. The method of claim 1 further including forming a first isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the first isolation region surrounds the fourth doped region and the first portion of the first doped region; and forming a second isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the second isolation region surrounds the second doped region and at least a portion of the third doped region.
5. A method of forming an integrated semiconductor device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first doped region of a second conductivity type on a surface of the semiconductor substrate;
forming a second doped region of the first conductivity type on a surface of the first doped region wherein the second doped region and the first doped region form a first diode;
forming a third doped region of the second conductivity type on the surface of the semiconductor substrate and underlying the second doped region wherein the third doped region and a first portion of the semiconductor substrate form a first zener diode;
forming a fourth doped region of the second conductivity type on the surface of the first doped region and spaced laterally apart from the second doped region wherein an interface between the semiconductor substrate and a first portion of the first doped region that underlies the fourth doped region forms a second diode;
forming a first isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the first isolation region has a periphery that surrounds an interface between the semiconductor substrate and a second portion of the first doped region wherein the second portion of the first doped region does not underlie the first, second, third, or fourth doped regions and wherein the interface between the semiconductor substrate and the second portion of the first doped region forms a third diode that is in parallel with the second diode;
forming a fifth doped region of the second conductivity type on the surface of the first doped region and spaced apart from the second and fourth doped regions wherein the fifth doped region overlies the second portion of the first doped region; and
forming a sixth doped region of the first conductivity type within the fifth doped region wherein an interface between the fifth and sixth doped regions forms a fourth diode.
6. The method of claim 5 further including forming a seventh doped region of the first conductivity type within the fifth doped region and spaced apart form the sixth doped region wherein an interface between the fifth and seventh doped regions forms a fifth diode.
7. A method of forming an integrated semiconductor device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first doped region of a second conductivity type on a surface of the semiconductor substrate;
forming a second doped region of the first conductivity type on a surface of the first doped region wherein the second doped region and the first doped region form a first diode;
forming a third doped region of the second conductivity type on the surface of the semiconductor substrate and underlying the second doped region wherein the third doped region and a first portion of the semiconductor substrate form a first zener diode;
forming a fourth doped region of the second conductivity type on the surface of the first doped region and spaced laterally apart from the second doped region wherein an interface between the semiconductor substrate and a first portion of the first doped region that underlies the fourth doped region forms a second diode; and
forming a first isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the first isolation region has a periphery that surrounds an interface between the semiconductor substrate and a second portion of the first doped region wherein the second portion of the first doped region does not underlie the first, second, third, or fourth doped regions and wherein the interface between the semiconductor substrate and the second portion of the first doped region forms a third diode that is in parallel with the second diode; and
forming a second isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the second isolation region surrounds the fourth doped region and the first portion of the first doped region; and forming a third isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the third isolation region surrounds the second doped region and at least a portion of the third doped region.
8. A method of forming an integrated semiconductor device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first doped region of a second conductivity type on a surface of the semiconductor substrate;
forming a second doped region of the first conductivity type on a surface of the first doped region wherein the second doped region and the first doped region form a first diode;
forming a third doped region of the second conductivity type on the surface of the semiconductor substrate and underlying the second doped region wherein the third doped region and a first portion of the semiconductor substrate form a first zener diode;
forming a fourth doped region of the second conductivity type on the surface of the first doped region and spaced laterally apart from the second doped region wherein an interface between the semiconductor substrate and a first portion of the first doped region that underlies the fourth doped region forms a second diode;
forming a first isolation region extending from the surface of the first doped region into the semiconductor substrate wherein the first isolation region has a periphery that surrounds an interface between the semiconductor substrate and a second portion of the first doped region wherein the second portion of the first doped region does not underlie the first, second, third, or fourth doped regions and wherein the interface between the semiconductor substrate and the second portion of the first doped region forms a third diode that is in parallel with the second diode; and
forming an inductor having a first terminal coupled to the first, second, and third diodes.