Power semiconductor device having improved performance and method
View Patent ↗In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a counter-doped drain region spaced apart from a channel region.
1. A semiconductor device, comprising:
a semiconductor substrate;
a semiconductor layer of a first conductivity type formed over the semiconductor substrate and having a major surface;
a body region of a second conductivity type disposed in the semiconductor layer for forming a channel of the semiconductor device;
a current conducting region of the first conductivity type formed in the body region;
a gate structure formed adjacent the channel;
a first doped region of the second conductivity type formed in the semiconductor layer in proximity to a drain edge of the channel to enhance breakdown voltage of the semiconductor device when in operation, wherein the first doped region is spaced apart from the body region so that a portion of the semiconductor layer is between the body region and the first doped region in proximity to the major surface;
a first conductive layer coupled to the first doped region;
a second doped region of the first conductivity type formed between the body region and the first doped region, wherein the second doped region has a higher dopant concentration than the semiconductor layer.
2. The semiconductor device of claim 1 further comprising a pedestal structure formed over the major surface, and wherein the gate structure includes a control electrode formed along a side surface of the pedestal structure.
3. The semiconductor device of claim 2 wherein the control electrode is extended over the pedestal structure to receive an external signal (V G ).
4. The semiconductor device of claim 1 wherein the semiconductor substrate comprises the second conductivity type.
5. The semiconductor device of claim 1 , wherein the first doped region and the current conducting region are biased at the same potential (V S ) when the semiconductor device is in operation.
6. The semiconductor device of claim 1 , wherein the first doped region is spaced a distance in a range from about 0.5 microns to about 3.0 microns from the body region.
7. The semiconductor device of claim 1 , wherein the substrate comprises the first conductivity type.
8. The semiconductor device of claim 1 , wherein the semiconductor layer comprises silicon-germanium.
9. The semiconductor device of claim 1 , wherein the semiconductor layer comprises silicon-germanium-carbon.
10. The semiconductor device of claim 1 , wherein the semiconductor device comprises a plurality of body regions to form a cellular design.
11. The semiconductor device of claim 1 , wherein the semiconductor device comprises a single body region to form a single body design.
12. An IGFET device comprising:
a semiconductor substrate;
a semiconductor layer of a first conductivity type formed overlying the semiconductor substrate and having a major surface;
a body region of a second conductivity type disposed in the semiconductor layer for forming a channel of the IGFET device;
a source region of the first conductivity type formed in the body region;
a gate structure comprising a gate dielectric layer and a conductive gate region formed adjacent the body region and source region for controlling the channel;
a first doped region of the second conductivity type formed in the semiconductor layer in proximity to a drain edge of the channel when in operation, wherein the first doped region is spaced apart from the body region so that a portion of the semiconductor layer is between the body region and the first doped region in proximity to the major surface; and
a first conductive layer electrically coupled to the first doped region a second doped region of the first conductivity type formed between the body region and the first doped region, wherein the second doped region has a higher dopant concentration than the semiconductor layer.
13. The IGFET device of claim 12 , wherein the first doped region and the source region are biased at the same potential (V S ) when the IGFET device is in operation.
14. The IGFET device of claim 12 , wherein the first doped region is spaced a distance in a range from about 0.5 microns to about 3.0 microns from the body region.
15. A semiconductor device comprising:
a semiconductor substrate;
a semiconductor layer of a first conductivity type formed overlying the semiconductor substrate and having a major surface;
a body region of a second conductivity type disposed in the semiconductor layer for forming a channel of the IGFET device;
a source region of the first conductivity type formed in the body region;
a gate structure comprising a gate dielectric layer and a conductive gate region formed adjacent the body region and source region for controlling the channel;
a first doped region of the second conductivity type formed in the semiconductor layer in proximity to a drain edge of the channel when in operation, wherein the first doped region is spaced apart from the body region so that a portion of the semiconductor layer is between the body region and the first doped region in proximity to the major surface;
a second doped region of the first conductivity type formed between the body region and the first doped region, wherein the second doped region has a higher dopant concentration than the semiconductor layer; and
a first conductive layer electrically coupled to the first doped region.
16. The semiconductor device of claim 15 wherein the semiconductor substrate comprises the second conductivity type.
17. The semiconductor device of claim 15 , wherein the first doped region and the source region are biased at the same potential (V S )when the semiconductor device is in operation.
18. The semiconductor device of claim 15 , wherein the first doped region is spaced a distance in a range from about 0.5 microns to about 3.0 microns from the body region.