Receiver circuit, application of a first and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal
View Patent ↗A receiver circuit, application of a first proportional element and a second proportional element of a digital PLL structure, and method for receiving a frequency-shift keyed signal are provided. A phase signal is calculated from an in-phase signal and a quadrature signal. A feedback signal is subtracted from the phase signal to form a difference signal. An output signal is determined from the difference signal by a nonlinear transfer function. The output signal is evaluated with an evaluation circuit. A first signal and a second signal are added to form a summation signal. The first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor. The second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and the feedback signal is produced by integration of the summation signal.
1. A receiver circuit, which has a demodulator for demodulation of a frequency-shift-keyed signal, the demodulator comprising:
a first transmission element that has an arctangent function for converting an in-phase signal and a quadrature signal into a phase signal;
a subtractor having a second input connected to an output of the first transmission element;
a second transmission element;
a first proportional element;
a first integrator;
a second proportional element; and
a second integrator connected to the second proportional element;
an adder connected to the second integrator;
wherein the second transmission element is connected to the subtractor, to at least the first proportional element and one output of the demodulator, and has a nonlinear transfer function,
wherein the first proportional element is connected to the adder,
wherein the first integrator is connected to the adder and a first input of the subtractor, and
wherein the output of the demodulator is connected to an evaluation circuit.
2. The receiver circuit according to claim 1 , wherein the input of the second proportional element is connected to the input or the output of the first proportional element.
3. The receiver circuit according to claim 1 , wherein the output of the demodulator is connected to a decimation filter of the evaluation circuit.
4. The receiver circuit according to claim 1 , wherein the first proportional element is designed for alterable setting of a first proportionality factor.
5. The receiver circuit according to claim 1 , wherein the second proportional element is designed for alterable setting of a second proportionality factor.
6. The receiver circuit according to claim 1 , wherein the second transmission element is designed for alterable setting of the transfer function.
7. A method for receiving a frequency-shift keyed signal, the method comprising:
calculating a phase signal from an in-phase signal and a quadrature signal;
subtracting a feedback signal from the phase signal to form a difference signal;
determining an output signal from the difference signal by a nonlinear transfer function;
evaluating the output signal with an evaluation circuit; and
adding a first signal and a second signal to form a summation signal;
wherein the first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor,
wherein the second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration, and
wherein the feedback signal is produced by integration of the summation signal.
8. The method according to claim 7 , wherein the output signal is first processed by a decimation filter for evaluation, and then the decimated signal is evaluated for data output.
9. The method according to claim 7 , wherein the first proportionality factor and/or the second proportionality factor are set in a time-dependent manner and/or as a function of the output signal.
10. The method according to claim 9 , wherein the first proportionality factor and the second proportionality factor are at least temporarily associated with one another and/or depend on one another by a function, wherein, the second proportionality factor is set equal to the square of the first proportionality factor.
11. The method according to claim 9 , wherein a first initial value of the first proportionality factor is greater than a value the first proportionality factor is later set to in a locked-in state, and/or wherein a second initial value of the second proportionality factor is greater than a value the second proportionality factor is later set to, in particular in a locked-in state.
12. The method according to claim 11 , wherein, for different received signals, the second initial value of the second proportionality factor is larger for a first number of sampling points per bit of a first received signal than for a second number of sampling points per bit of a second received signal, if the first number of sampling points per bit is smaller then the second number of sampling points per bit.
13. The method according to claim 11 , wherein the first initial value is 1 and/or wherein the second initial value is ¾, ½, ⅜, ¼ or ⅛ and/or wherein the first proportionality factor and/or the second proportionality factor is switched in steps for setting.
14. The method according to claim 7 , wherein the first proportionality factor and/or the second proportionality factor are set to smaller values in a stepwise manner, in particular until a predefinable first target value of the first proportionality factor is reached and/or until a predefinable second target value of the second proportionality factor is reached.
15. The method according to claim 7 , wherein for different received signals a second target value of the second proportionality factor is larger for a first ratio of data rate to sample rate for a first received signal than for a second ratio of data rate to sample rate for a second received signal, if the first ratio is larger than the second ratio.
16. The method according to claim 7 , wherein an offset of the difference signal or a signal that at least temporarily correlates therewith is determined.
17. The method according to claim 16 , wherein the first proportionality factor is set depending on the detected offset.
18. A system, comprising:
means for calculation a phase signal from an in-phase signal and a quadrature signal;
means for subtracting a feedback signal from the phase signal to form a difference signal;
means for determining an output signal from the difference signal by a nonlinear transfer function;
means for evaluating the output signal with an evaluation circuit; and
means for adding a first signal and a second signal to form a summation signal;
wherein:
the first signal is produced by multiplication of the output signal or the difference signal by a first proportionality factor;
the second signal is produced by multiplication of the output signal or the first signal or the difference signal by a second proportionality factor, followed by integration; and
the feedback signal is produced by integration of the summation signal.
19. The system according to claim 18 , wherein the output signal is first processed by a decimation filter for evaluation, and then the decimated signal is evaluated for data output.
20. The system according to claim 18 , wherein for different received signals a second target value of the second proportionality factor is larger for a first ratio of data rate to sample rate for a first received signal than for a second ratio of data rate to sample rate for a second received signal, if the first ratio is larger than the second ratio.