Resist feature and removable spacer pitch doubling patterning method for pillar structures

1. A method of making a semiconductor device, comprising:

forming at least one layer over a substrate;

forming at least two spaced apart features of imagable material over the at least one layer, wherein the at least two spaced apart features comprise a plurality of features;

forming sidewall spacers on the plurality of features, such that the sidewall spacers on adjacent features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers;

filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature;

selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other; and

etching the at least one layer using the first feature, the filler feature and the second feature as a mask.

2. The method of claim 1 , further comprising:

filling each space between each two adjacent features of the plurality of features with one of a plurality of filler features; and

etching the at least one layer using the plurality of features and the plurality of filler features as a mask.

3. The method of claim 1 , wherein:

the at least two features and the filler feature comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing comprises selectively etching the second material of the sidewall spacers without substantially removing the first material.

4. The method of claim 1 , wherein:

the at least two features comprise a first material, the filler feature comprises a second material and the sidewall spacers comprise a third material different from the first and the second material; and

the step of selectively removing the sidewall spacers comprises selectively etching the third material of the sidewall spacers without substantially removing the first or the second material.

5. The method of claim 1 , wherein the step of filling the space between the first sidewall spacer on the first feature and the second sidewall spacer on the second feature with the filler feature comprises depositing a flowable polymer filler material by liquid phase deposition over the first and the second features such that upper portions of the sidewall spacers are exposed.

6. The method of claim 1 , wherein:

the imagable material comprises a photoresist material, an electron beam resist material or a nanoimprint resist material;

the filler feature comprises a flowable polymer material having a viscosity of about 1 to about 15 centipose; and

the step of selectively removing the sidewall spacers comprises selectively etching the sidewall spacers without substantially removing the at least two spaced apart features and the filler feature.

7. The method of claim 6 , wherein:

the at least two features and the filler feature comprise a photoresist material; and

the sidewall spacers comprise silicon oxide.

8. The method of claim 1 , wherein:

the at least two features and the filler features comprise a photoresist material; and

the sidewall spacers comprise silicon nitride.

9. The method of claim 1 , further comprising removing the at least two features and the filler feature after the step of etching the at least one layer.

10. The method of claim 1 , further comprising trimming the at least two features to reduce size of the at least two features, prior to the step of forming sidewall spacers on the at least two features.

11. The method of claim 1 , wherein the at least one layer comprises a hard mask stack located over at least one semiconductor device layer.

12. The method of claim 11 , wherein the hard mask stack comprises a BARC layer, a DARC layer, an organic hard mask layer, and at least one conductive hard mask layer.

13. The method of claim 12 , wherein the step of etching the at least one layer comprises etching at least the DARC layer.

14. The method of claim 13 , further comprising trimming the DARC layer to form DARC layer portions having a substantially cylindrical shape.

15. The method of claim 13 , further comprising:

removing the at least two features and the filler feature after the step of etching the DARC layer;

etching at least the organic hard mask layer using the etched DARC layer as a mask; and

etching the at least one semiconductor layer using at least one of the organic hard mask layer and the conductive hard mask layer as a mask.

16. The method of claim 15 , wherein the step of etching the at least one semiconductor device layer forms a plurality of pillar shaped devices.

17. The method of claim 16 , wherein the plurality of pillar shaped devices comprise a plurality of nonvolatile memory cells each comprising a diode steering element and a resistivity switching storage element.

18. A method of making a pillar shaped nonvolatile memory device array, comprising:

forming a plurality of bottom electrodes over a substrate;

forming at least one device layer comprising at least one steering element layer and at least one storage element layer over the plurality of bottom electrodes;

forming a hard mask stack over the at least one device layer;

forming a plurality of photoresist spaced apart features over the hard mask stack;

forming sidewall spacers on the plurality of photoresist spaced apart features;

forming a plurality of photoresist filler features between the plurality of photoresist spaced apart features such that upper portions of the sidewall spacers are exposed and such that the plurality of photoresist filler features are located between the sidewall spacers;

selectively removing the sidewall spacers to leave the plurality of photoresist spaced apart features and the plurality of photoresist filler features spaced apart from each other;

etching at least a portion of the hard mask stack using the plurality of photoresist spaced apart features and the plurality of photoresist filler features as a mask to form a plurality of hard mask features;

etching the at least one device layer using the plurality of hard mask features as a mask, to form a plurality of pillar shaped nonvolatile memory cells each comprising a diode steering element and a resistivity switching storage element; and

forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells.

19. A method of making a semiconductor device, comprising:

forming a layer over a substrate, wherein the layer comprises a hard mask stack located over a semiconductor device layer, wherein the hard mask stack comprises a BARC layer, a DARC layer, an organic hard mask layer, and a conductive hard mask layer;

forming a plurality of spaced apart features of imagable material over the layer;

forming sidewall spacers on the plurality of features;

filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature;

selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other; and

etching the layer using the first feature, the filler feature and the second feature as a mask.

20. The method of claim 19 , wherein etching the layer comprises etching the DARC layer.

21. The method of claim 20 , further comprising trimming the DARC layer to form DARC layer portions having a substantially cylindrical shape.

22. The method of claim 20 , further comprising:

removing the plurality of features and the filler feature after the step of etching the DARC layer;

etching the organic hard mask layer using the etched DARC layer as a mask; and

etching the semiconductor device layer using at least one of the organic hard mask layer and the conductive hard mask layer as a mask.

23. The method of claim 22 , wherein etching the semiconductor device layer forms a plurality of pillar shaped devices.

24. The method of claim 23 , wherein the plurality of pillar shaped devices comprise a plurality of nonvolatile memory cells each comprising a diode steering element and a resistivity switching storage element.