Method of fabricating a vertical transistor and capacitor
View Patent ↗A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.
1. A process for fabricating an integrated circuit structure comprising:
forming a first device region selected from the group consisting of a source region and a drain region of a semiconductor device in a semiconductor substrate;
forming a multilayer stack comprising at least three layers of material over the first device region in the semiconductor substrate wherein the second layer is interposed between the first and the third layers, and wherein the first layer is adjacent the first device region
forming a first and a second window in the at least three layers of material, wherein said first and second windows terminate at the first device region;
forming doped semiconductor material in the first window, thereby forming a doped semiconductor plug in the at least three layers of material, wherein the doped semiconductor plug has a first end and a second end, and wherein the first end is in contact with the first device region;
forming a second device region selected from the group consisting of a source region and a drain region in the second end of the doped semiconductor plug, wherein one of the first and second device regions is a source region and the other is a drain region;
removing the second layer, thereby exposing a portion of the doped semiconductor plug;
forming gate dielectric material on the exposed portion of the first semiconductor plug;
forming a gate in contact with the gate dielectric material;
forming a first conductive layer in the second window;
forming a first dielectric layer overlying the first conductive layer in the second window; and
forming a second conductive layer over the first dielectric layer in the second window, such that the first conductive layer, the first dielectric layer and the second conductive layer form a capacitor.
2. The process of claim 1 wherein the second layer is removed by etching in an etchant, characterized by a first layer etch rate, a second layer etch rate, and a third layer etch rate, and wherein the second layer etch rate is at least ten times faster than one of the first layer etch rate and the third layer etch rate.
3. The process of claim 2 wherein the etchant is selected from the group consisting of isotropic wet etchants and isotropic dry etchants.
4. The process of claim 1 wherein the material of the first layer and the third layer is an electrically insulating material is selected from the group consisting of silicon nitride, silicon dioxide, and doped silicon dioxide.
5. The process of claim 1 wherein the material of the first and the third layers comprises doped silicon dioxide, and wherein the process further comprises further doping the doped semiconductor plug with dopant from the first layer and the third layer to form doped extension regions in the doped semiconductor plug.
6. The process of claim 5 wherein the dopant type in the doped silicon dioxide is selected from the group consisting of n-type and p-type, and wherein the dopant type is opposite the dopant type in the doped semiconductor plug.
7. The process of claim 1 wherein the semiconductor plug material comprises a crystalline semiconductor material and is selected from the group consisting of silicon, silicon-germanium, and silicon-germanium-carbon.
8. The process of claim 1 further comprising forming an etch stop layer over either the first layer of material or the second layer of material, or over both the first and the second layers of material.
9. The process of claim 1 further comprising forming a diffusion barrier layer over the first device region before the at least three layers of material are formed thereover.
10. The process of claim 1 wherein the gate is formed from a material selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped polycrystalline silicon-germanium, doped amorphous silicon-germanium, doped polycrystalline silicon-germanium-carbon, doped amorphous silicon-germanium-carbon, metals and metal-containing compounds.
11. The process of claim 1 wherein the gate comprises a first and second segment, and wherein the first segment is formed in a region vacated by removal of the second layer in the area of the first window such that the first segment is adjacent the gate dielectric, and wherein the second segment is formed in the region vacated by removal of the second layer in the area of the second window such that the second segment is adjacent the first conductive layer in the second window, such that the gate dielectric material is electrically connected to a plate of the capacitor.
12. The process of claim 11 further comprising forming an insulative layer between the first and the second segments of the gate to isolate the gate dielectric material from the capacitor.
13. The process of claim 1 wherein the first and second conductive layers formed in the second window are formed from a material selected from the group consisting of doped polycrystalline silicon, doped amorphous silicon, doped polycrystalline silicon-germanium, doped amorphous silicon-germanium, doped polycrystalline silicon-germanium-carbon, doped amorphous silicon-germanium-carbon, metals and metal containing compounds.
14. The process of claim 1 wherein the first dielectric layer comprises material selected from the group consisting of silicon dioxide and silicon nitride.