Radiation tolerant SRAM bit

1. In integrated circuit, a radiation tolerant static random access memory device comprising:

a first pair of complementary transistors having an input and an output, said first pair of complementary transistors connected in series between a first voltage potential and a second voltage potential through a first node that provides the output for the first pair, and a gate of each of the first pair connected together as the input to the first pair of complementary transistors;

a second pair of complementary transistors having an input and an output, said second pair of complementary transistors connected in series between the first voltage potential and the second voltage potential through a second node that provides the output for the second pair, and a gate of each of the second pair connected together as the input to the second pair, said output of said first pair of complementary transistors coupled to said input of said second pair of complementary transistors and said output of said second pair of complementary transistors coupled to said input of said first pair of complementary transistors;

a first resistor coupled between said first and second pairs of complementary transistors; and

wherein:

an RC time constant of the radiation tolerant static random access memory device exceeds a selected recovery time of the s radiation tolerant static random access memory device.

2. The radiation tolerant static random access memory device in claim 1 wherein:

the first voltage potential is higher than the second voltage potential,

the first pair of complementary transistors and the second pair of complementary transistors each form an inverter comprising:

a p-type transistor coupled between the first voltage potential and an n-type transistor, and

the n-type transistor coupled between the p-type transistor and the second voltage potential.

3. The radiation tolerant static random access memory device in claim 1 wherein:

the first resistor has a resistance of approximately 4M ohms.

4. The radiation tolerant static random access memory device in claim 1 wherein:

the selected recovery time is long enough to negate an effect of a high-energy particle impact on the radiation tolerant static random access memory device.

5. The radiation tolerant static random access memory device in claim 1 which further comprises:

a first write transistor coupled to said output of said first pair of complementary transistors and having a gate coupled to a source of write-control signals; and

a second write transistor coupled to said output of said second pair of complementary transistors and having a gate coupled to said source of write-control signals.

6. The radiation tolerant static random access memory device in claim 5 wherein:

the gate of the first write transistor and the gate of the second write transistor are coupled to a word line;

the first write transistor is coupled between the output of said first pair of complementary transistors and a first bit line; and

the second write transistor is coupled between the output of the second pair of complementary transistors and a second bit line.

7. The radiation tolerant static random access memory device in claim 1 which further comprises:

a second resistor coupled between said second and first pairs of complementary transistors.

8. The radiation tolerant static random access memory device in claim 7 wherein:

the first resistor and the second resistor have a cumulative resistance of approximately 4M ohms.

9. The radiation tolerant static random access memory device in claim 1 wherein:

the first voltage potential is V cc ; and

the second voltage potential is ground.

10. The radiation tolerant static random access memory device in claim 1 which further comprises:

a pass transistor having a gate coupled to the output of a first one of said first pair and said second pair of complementary transistors.

11. In a integrated circuit, a method of producing a radiation tolerant static random access memory device comprising:

providing a first pair of complementary transistors having an input and an output,

connecting said first pair of complementary transistors in series between a first voltage potential and a second voltage potential through a first node that provides the output for the first pair,

connecting a gate of each of the first pair together as the input to the first pair of complementary transistors;

providing a second pair of complementary transistors having an input and an output,

connecting said second pair of complementary transistors in series between the first voltage potential and the second voltage potential through a second node that provides the output for the second pair,

connecting a gate of each of the second pair together as the input to the second pair,

coupling said output of said first pair of complementary transistors to said input of said second pair of complementary transistors and said output of said second pair of complementary transistors to said input of said first pair of complementary transistors; and

coupling a first resistor between said first and second pairs of complementary transistors;

wherein:

an RC time constant of the radiation tolerant static random access memory device exceeds a selected recovery time of the s radiation tolerant static random access memory device.

12. The method in claim 11 wherein:

the first voltage potential is higher than the second voltage potential,

the first pair of complementary transistors and the second pair of complementary transistors each form an inverter comprising:

a p-type transistor coupled between the first voltage potential and an n-type transistor, and

the n-type transistor coupled between the p-type transistor and the second voltage potential.

13. The method in claim 11 wherein:

the first resistor has a resistance of approximately 4M ohms.

14. The method in claim 11 wherein:

the selected recovery time is long enough to negate the effect of a high-energy particle impact on the radiation tolerant static random access memory device.

15. The method in claim 11 which further comprises:

providing a first write transistor having a gate, a first node, and a second node;

coupling a first node of the first write transistor to said output of said first pair of complementary transistors;

coupling the gate of the first write transistor to a source of write-control signals;

providing a second write transistor having a gate, a first node, and a second node;

coupling said output of said second pair of complementary transistors to the first node of the second write transistor; and

coupling the gate of said second write transistor to said source of write-control signals.

16. The method in claim 15 which further comprises:

coupling the gate of the first write transistor and the gate of the second write transistor to a word line;

coupling the second node of first write transistor to a first bit line; and

coupling the second node of the second write transistor to a second bit line.

17. The method in claim 11 which further comprises:

coupling a second resistor between said second and first pairs of complementary transistors.

18. The method in claim 17 wherein:

the first resistor and the second resistor have a cumulative resistance of approximately 4M ohms.

19. The method in claim 11 wherein:

the first voltage potential is V cc ; and

the second voltage potential is ground.

20. The method in claim 11 which further comprises:

providing a pass transistor having a gate;

coupling the gate of the pass transistor to the output of a one of said first pair and said second pair of complementary transistors.