Clustered field programmable gate array architecture
View Patent ↗A logic cluster for a field programmable gate array integrated circuit device is disclosed. The cluster comprises a plurality of functional blocks and three levels of routing multiplexers. External signals enter the logic cluster primarily at the third level multiplexers with a few signals entering at the second level. Combinational outputs are fed back into the first and second level multiplexers while sequential outputs are fed back into the third level multiplexers. The logic function generators have permutable inputs with varying propagation delays. Routing signals between the first and second level multiplexers are grouped into speed classes and coupled to first level multiplexers associated with different logic function generators according to their speed class. Second and third level multiplexers are organized into groups such that routing signals between the second and third level multiplexers can be localized within the area occupied by the group. Groups are pitch matched to logic function generators to optimize and modularize area. Provision is made for global and local control of the sequential elements.
1. A logic cluster for a field programmable gate array integrated circuit device, comprising:
(a) a plurality of functional blocks each having a plurality of inputs and at least one output;
(b) a first level of multiplexers, each multiplexer having:
(i) a plurality of data channels, and
(ii) an output coupled to exactly one of the functional block inputs;
(c) a second level of multiplexers, each multiplexer having:
(i) a plurality of data channels, and
(ii) an output;
(d) a third level of multiplexers, each multiplexer having:
(i) a plurality of data channels, and
(ii) an output;
(e) a plurality of external interconnects, each interconnect being coupled to at least one third level multiplexer data channel;
(f) a first plurality of internal interconnects, each interconnect being coupled between one second level multiplexer output and at least one first level multiplexer data channel;
(g) a second plurality of internal interconnects, each interconnect being coupled between one third level multiplexer output and at least one second level multiplexer data channel;
(h) a first plurality of feedback interconnects, each interconnect being coupled between one functional block output and at least one second level multiplexer data channel; and
(i) a second plurality of feedback interconnects, each interconnect being coupled between one functional block output and at least one third level multiplexer data channel associated with a fastest one of the first level of multiplexers.
2. The logic cluster of claim 1 , wherein:
(a) each functional block has a combinational output and a sequential output;
(b) each interconnect of the first plurality of feedback interconnects is coupled to a functional block combinational output; and
(c) each interconnect of the second plurality of feedback interconnects is coupled to a functional block sequential output.
3. The logic cluster of claim 2 , further comprising a third plurality of feedback interconnects, each interconnect being coupled between a functional block combinational output and at least one first level multiplexer data channel.
4. The logic cluster of claim 3 , wherein at least one of the external interconnects is further coupled to at least one second multiplexer data channel.
5. The logic cluster of claim 2 , wherein at least one of the external interconnects is further coupled to at least one second multiplexer data channel.
6. A logic cluster for a field programmable gate array integrated circuit device having a plurality of speed classes, each speed class comprising a group of select signal paths, having a propagation delay substantially different from the propagation delay of the select signal paths of every other speed class, the logic cluster comprising:
(a) a plurality of functional blocks, each with a plurality of logic inputs, a plurality of sequential control inputs, a combinational output, and a sequential output, wherein:
(i) the propagation delay from each logic input to the combinational output is substantially different from the propagation delay from every other input to the combinational output,
(ii) each logic input is traversed by the select signal paths of exactly one speed class, and
(iii) each logic input is traversed by the select signal paths of a different speed class;
(b) a first level of multiplexers, each multiplexer having a plurality of data channels and an output, wherein:
(i) each of the multiplexers in the first plurality of multiplexers having its output coupled to exactly one of the logic inputs in the plurality of functional blocks, and
(ii) the number of multiplexers in the first plurality of multiplexers is equal to the number of logic inputs in the plurality of functional blocks;
(c) a second level of multiplexers, each multiplexer having a plurality of data channels and an output;
(d) a third level of multiplexers, each multiplexer having a plurality of data channels and an output;
(e) a plurality of external interconnects, each interconnect being coupled to at least one third level multiplexer data channel;
(f) a first level of internal interconnects, each interconnect being coupled between one second level multiplexer output and at least one first level multiplexer data channel; and
(g) a second level of internal interconnects, each interconnect being coupled between one third level multiplexer output and at least one second level multiplexer data channel, wherein each select signal path
(i) originates at the input of second level multiplexer data channel, and
(ii) terminates at a functional block combinational output.
7. The logic cluster of claim 6 , wherein:
(a) each of the first level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(b) each of the first level internal interconnects is traversed by a subset of the select signal paths of exactly one speed class;
(c) each of the second level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(d) the propagation delays of the select signal paths in each speed class are substantially different from the propagation delays of the select signal paths in each of the other speed classes; and
(e) each functional block logic input having the smallest propagation delay to the combinational output of the same functional block is traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.
8. The logic cluster of claim 7 , wherein one of the external interconnects is further coupled to a second level multiplexer data channel traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.
9. The logic cluster of claim 6 , further comprising:
(a) a first plurality of feedback interconnects each coupling a functional block combinational output to at least one second level multiplexer data channel; and
(b) a second plurality of feedback interconnects each coupling a functional block sequential output to at least one third level multiplexer data channel.
10. The logic cluster of claim 9 , wherein:
(a) each of the first level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(b) each of the first level internal interconnects is traversed by a subset of the select signal paths of exactly one speed class;
(c) each of the second level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(d) the propagation delays of the select signal paths in each speed class are substantially different from the propagation delays of the select signal paths in each of the other speed classes; and
(e) each functional block logic input having the smallest propagation delay to the combinational output of the same functional block is traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.
11. The logic cluster of claim 10 , wherein one of the external interconnects is further coupled to a second level multiplexer data channel traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.
12. The logic cluster of claim 6 , further comprising a third plurality of feedback interconnects each feedback interconnect coupling a functional block combinational output to a first level multiplexer data channel.
13. The logic cluster of claim 12 , wherein:
(a) each of the first level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(b) each of the first level internal interconnects is traversed by a subset of the select signal paths of exactly one speed class;
(c) each of the second level multiplexers is traversed by a subset of the select signal paths of exactly one speed class;
(d) the propagation delays of the select signal paths in each speed class are substantially different from the propagation delays of the select signal paths in each of the other speed classes; and
(e) each functional block logic input having the smallest propagation delay to the combinational output of the same functional block is traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.
14. The logic cluster of claim 13 , wherein one of the external interconnects is further coupled to a second level multiplexer data channel traversed by a subset of the select signal paths of the speed class with the smallest propagation delay.