Copper deposition for filling features in manufacture of microelectronic devices
View Patent ↗A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper wettable metal to fill the feature with copper.
1. A method for metallizing an electrical interconnect feature with copper, the electrical interconnect feature being located in a dielectric material on a semiconductor integrated circuit device substrate, wherein the dielectric material has a top-field surface and the electrical interconnect feature has a bottom, a sidewall having a depth and a top opening having an opening dimension, the method comprising:
forming a deposit on the bottom and the sidewall of the electrical interconnect feature, the deposit comprising a copper wettable metal;
forming a copper-based deposit on the top-field surface;
forming an initial metal profile in the electrical interconnect feature, the initial metal profile comprising copper metal deposited on the bottom of the electrical interconnect feature and a segment of the sidewall having essentially no copper metal thereon, wherein the initial metal profile is formed by (i) depositing a copper seed layer on the bottom and the sidewall of the interconnect feature and (ii) dissolving a portion of the copper seed layer to thereby form the initial metal profile;
partially filling the interconnect feature by electrolytic Cu deposition between said (i) depositing the copper seed layer on the bottom and the sidewall of the interconnect feature and said (ii) dissolving the portion of the copper seed layer; and
filling the electrical interconnect feature having the initial metal profile with copper to thereby metallize the electrical interconnect feature .
2. The method of claim 1 wherein the electrical interconnect feature is filled with copper by contacting the substrate with an electrolytic copper deposition composition and applying an external source of electrons to thereby metallize the interconnect feature with electrolytically deposited copper.
3. The method of claim 1 wherein the copper wettable metal is selected from the group consisting of ruthenium, iridium, and cobalt.
4. The method of claim 1 wherein the opening dimension is between about 10 nm and about 500 nm.
5. The method of claim 1 wherein the depth is between about 200 nm to about 2000 nm.
6. The method of claim 1 wherein the electrical interconnect feature is filled with copper by contacting the substrate with an electroless copper deposition composition to thereby metallize the interconnect feature with electrolessly deposited copper.
7. The method of claim 1 wherein the copper wettable metal is ruthenium.
8. The method of claim 1 wherein the copper wettable metal is iridium.
9. The method of claim 1 wherein the copper wettable metal is cobalt.
10. The method of claim 1 wherein the portion of the copper seed layer is dissolved by anodic dissolution.
11. The method of claim 1 comprising:
in sequence,
said forming said deposit of copper wettable metal, wherein said forming said deposit is by a process selected from the group consisting of physical vapor deposition (PVD), plasma-enhanced physical vapor deposition (PE-PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD), wherein the copper wettable metal is ruthenium;
said forming the copper-based deposit on the top-field surface and the copper seed layer on the bottom and the sidewall of the interconnect feature, wherein said forming comprises a process selected from the group consisting of physical vapor deposition (PVD), plasma-enhanced physical vapor deposition (PE-PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD);
said partially filling the interconnect feature by electrolytic Cu deposition;
said dissolving the portion of the copper seed layer to thereby form said initial metal profile comprising the copper metal deposited on the bottom of the electrical interconnect feature and the segment of the sidewall having essentially no copper thereon, wherein said dissolving the portion of the copper seed layer is performed by anodic dissolution; and
said filling the electrical interconnect feature having the initial metal profile therein with the copper to thereby metallize the electrical interconnect feature.
12. The method of claim 11 wherein said copper-based deposit on the top-field surface is formed by a) said process selected from the group consisting of physical vapor deposition (PVD), plasma-enhanced physical vapor deposition (PE-PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD), followed by b) electrolytic deposition.
13. The method of claim 11 wherein said filling the electrical interconnect feature having the initial metal profile therein with the copper to thereby metallize the electrical interconnect feature is performed by electroless Cu deposition.
14. The method of claim 11 wherein the anodic dissolution dissolves said copper based deposit on the top-field surface in addition to said dissolving the portion of the copper seed layer.
15. The method of claim 11 wherein the electrical interconnect feature is filled with copper by contacting the substrate with an electrolytic copper deposition composition and applying an external source of electrons to thereby metallize the interconnect feature with electrolytically deposited copper.
16. A method for metallizing an electrical interconnect feature with copper, the electrical interconnect feature being located in a dielectric material on a semiconductor integrated circuit device substrate, wherein the dielectric material has a top-field surface and the electrical interconnect feature has a bottom, a sidewall having a depth and a top opening having an opening dimension, the method comprising:
in sequence,
forming a deposit of copper wettable metal, wherein said forming said deposit is by a process selected from the group consisting of physical vapor deposition (PVD), plasma-enhanced physical vapor deposition (PE-PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD), wherein the copper wettable metal is ruthenium;
forming a copper-based deposit on the top-field surface and a copper seed layer on the bottom and the sidewall of the interconnect feature, wherein said forming comprises a process selected from the group consisting of physical vapor deposition (PVD), plasma-enhanced physical vapor deposition (PE-PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD);
partially filling the interconnect feature by electrolytic Cu deposition;
dissolving a portion of the copper seed layer to thereby form an initial metal profile comprising copper metal deposited on the bottom of the electrical interconnect feature and a segment of the sidewall having essentially no copper thereon, wherein said dissolving is performed by anodic dissolution, and wherein said dissolving also dissolves said copper based deposit on the top-field surface in addition to said dissolving the portion of the copper seed layer; and
filling the electrical interconnect feature having the initial metal profile therein with copper to thereby metallize the electrical interconnect feature, wherein said filling comprises electroless Cu deposition.