Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor
View Patent ↗Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
1. A method of forming a field effect transistor, said method comprising:
providing a wafer comprising: a substrate, an insulator layer on said substrate and a single crystalline semiconductor layer on said insulator layer;
performing a first etch process to form recesses in said single crystalline semiconductor layer on opposing sides of a designated channel region such that sidewalls of said recesses adjacent to said channel region have a first profile and such that bottom surfaces of said recesses are separated from said insulator layer by a distance; and
performing a second etch process comprising selectively etching said sidewalls over said bottom surfaces so as to change said first profile to a second profile different from said first profile, while keeping said distance essentially the same.
2. The method of claim 1 , said distance comprising at least 10 nm.
3. The method of claim 1 further comprising:
after said performing of said first etch process and before said performing of said second etch process, implanting a dopant into said single crystalline semiconductor layer through said bottom surfaces of said recesses so to form, within said single crystalline semiconductor layer immediately adjacent to and aligned with said bottom surfaces, amorphous regions each having a thickness that is less than said distance such that said amorphous regions do not contact said insulator layer, wherein said selectively etching of said sidewalls over said bottom surfaces comprises etching said single crystalline semiconductor layer at said sidewalls selective to said amorphous regions at said bottom surfaces; and
after said performing of said second etch process, performing an anneal process to re-crystallize said amorphous regions.
4. The method of claim 3 ,
said dopant comprising any of Silicon, Germanium, Xenon, Argon, Nitrogen, Fluorine, Carbon, Sulfur, Oxygen, Neon, Krypton, Boron and Indium; and,
said method further comprising, after said performing of said anneal process, performing an epitaxial growth process to fill said recesses with Silicon Germanium to form source/drain regions for a p-type field effect transistor.
5. The method of claim 3 ,
said dopant comprising any of Silicon, Germanium, Xenon, Argon, Nitrogen, Fluorine, Carbon, Sulfur, Oxygen, Neon, Krypton, Arsenic, Phosphorous and Antimony; and,
said method further comprising, after said performing of said anneal process, performing an epitaxial growth process to fill said recesses with Silicon Carbide to form source/drain regions for an n-type field effect transistor.
6. The method of claim 1 , said semiconductor layer having a thickness of less than approximately 45 nm.
7. The method of claim 1 , said first etch process comprising any one of an isotropic etch process and an anisotropic etch process.
8. A method of forming a field effect transistor, said method comprising:
providing a wafer comprising: a substrate, an insulator layer on said substrate and a single crystalline semiconductor layer on said insulator layer;
performing a first etch process to form recesses in said single crystalline semiconductor layer on opposing sides of a designated channel region such that sidewalls of said recesses adjacent to said channel region have a first profile and such that bottom surfaces of said recesses are separated from said insulator layer by a distance of at least 10 nm;
after said performing of said first etch process, implanting a dopant into said single crystalline semiconductor layer through said bottom surfaces of said recesses so to form, within said single crystalline semiconductor layer immediately adjacent to and aligned with said bottom surfaces, amorphous regions each having a thickness that is less than approximately 10 nm such that said amorphous regions do not contact said insulator layer;
after said implanting, performing a second etch process comprising etching said single crystalline semiconductor layer at said sidewalls selective to said amorphous regions at said bottom surfaces so as to change said first profile to a second profile different from said first profile, while keeping said distance essentially the same, said second profile comprising a faceted profile; and
after said performing of said second etch process, performing an anneal process to re-crystallize said amorphous regions.
9. The method of claim 8 ,
said dopant comprising any of Silicon, Germanium, Xenon, Argon, Nitrogen, Fluorine, Carbon, Sulfur, Oxygen, Neon, Krypton, Indium and Boron; and,
said method further comprising, after said performing of said anneal process, performing an epitaxial growth process to fill said recesses with Silicon Germanium to form source/drain regions for a p-type field effect transistor.
10. The method of claim 8 ,
said dopant comprising any of Silicon, Germanium, Xenon, Argon, Nitrogen, Fluorine, Carbon, Sulfur, Oxygen, Neon, Krypton, Arsenic, Phosphorous and Antimony; and,
said method further comprising, after said performing of said anneal process, performing an epitaxial growth process to fill said recesses with Silicon Carbide to form source/drain regions for an n-type field effect transistor.
11. The method of claim 8 , said semiconductor layer having a thickness of less than approximately 45 nm.
12. The method of claim 8 , said first etch process comprising any one of an isotropic etch process and an anisotropic etch process.
13. The method of claim 8 , said implanting comprising performing a gas cluster ion beam implantation process so as to implant only exposed lateral surfaces of said single crystalline semiconductor layer.