Iterative write pausing techniques to improve read latency of memory systems

1. A phase change memory (PCM) device comprising:

a plurality of PCM memory locations; and

a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command including data to be written, the executing comprising:

initiating the iterative write;

updating a state of the iterative write;

pausing the iterative write including saving the state in response to receiving a pause command; and

resuming the iterative write in response to receiving a resume command, the resuming responsive to the saved state and to the data to be written.

2. The memory device of claim 1 , wherein the resuming comprises:

retrieving the data to be written;

retrieving the saved state;

reinitializing the mechanism for executing the iterative write responsive to the retrieved state and to the data to be written; and

restarting the iterative write.

3. The memory device of claim 2 , wherein the iterative write includes applying one or more pulses to program a memory location.

4. The memory device of claim 3 , wherein the pulses comprise melting pulses and the state includes parameters of the last applied melting pulse.

5. The memory device of claim 3 , wherein the pulses comprise melting pulses and wherein the resuming includes restarting the iterative write from the last applied melting pulse at each of the memory locations being programmed by the write command.

6. The memory device of claim 1 , wherein the state is comprised of one or more of (a) a set of parameters describing a model for each memory location being programmed by the write command, (b) a counter of the number of iterations applied to each memory location being programmed by the write command, (c) a timestamp indicating the time of a last applied programming pulse to each memory location being programmed by the write command, and (d) a value of a read resistance of each memory location being programmed by the write command.

7. The memory device of claim 1 , wherein the iterative write includes a verify step after an application of a programming pulse, and wherein the pausing takes effect after the verify step.

8. The memory device of claim 1 , wherein the mechanism further stores timing information in response to the completion of the iterative write and wherein a subsequent read operation to the one or more memory locations being programmed by the write command is prevented if the time of the subsequent read operation is less than the timing information.

9. The memory device of claim 1 , wherein the memory locations are subject to a resistance drift process and wherein the mechanism further causes a pulse to be applied to each of the memory locations being programmed by the write command to restart the resistance drift process in response to receiving the resume command.

10. The memory device of claim 1 , wherein restarting the iterative write includes reading contents of the memory locations being programmed by the write command.

11. A memory system comprising:

one or more phase change memory (PCM) devices comprising:

a plurality of memory locations; and

a mechanism for executing iterative writes to the memory locations, for interrupting iterative writes that are executing, and for saving a state of any interrupted iterative writes; and

a memory controller in communication with the memory devices and comprising a mechanism for requesting an interruption to an iterative write, the requesting responsive to an elapsed execution time of the iterative write.

12. The memory system of claim 11 , wherein the memory controller stores a programmable threshold and wherein the interruption is requested if the elapsed execution time is less than the threshold.

13. The memory system of claim 11 , further comprising a write queue for storing pending write commands and wherein the requesting is further responsive to the number of pending write commands.

14. The memory system of claim 13 , wherein the memory controller stores an adaptive threshold that is responsive to the number of pending write commands and wherein the interruption is requested if the elapsed execution time is less than the adaptive threshold.

15. The memory system of claim 11 , wherein the interruption requested is an abort.

16. The memory system of claim 11 , wherein the interruption requested is a pause.

17. A computer implemented method for writing to memory, the method comprising:

receiving a write command at a memory system, the write command including data to be written and specifying a plurality of memory locations; and

executing an iterative write to the memory locations in response to receiving the write command, the executing comprising:

initiating the iterative write;

updating a state of the iterative write;

pausing the iterative write including saving the state in response to receiving a pause command; and

resuming the iterative write in response to receiving a resume command, the resuming responsive to the saved state and to the data to be written.

18. The method of claim 17 , wherein the resuming comprises:

retrieving the data to be written;

retrieving the saved state;

reinitializing the mechanism for executing the iterative write responsive to the retrieved state and to the data to be written; and

restarting the iterative write.

19. The method of claim 17 , wherein the memory system is a phase change memory (PCM) device and the iterative write includes applying one or more pulses to program a memory location.

20. The method of claim 19 , wherein the pulses comprise melting pulses and the state includes parameters of the last applied melting pulse.

21. The method of claim 19 , wherein the pulses comprise melting pulses and wherein the resuming includes restarting the iterative write from the last applied melting pulse at each of the memory locations being programmed by the write command.

22. The method of claim 17 , wherein the state is comprised of one or more of (a) a set of parameters describing a model for each memory location being programmed by the write command, (b) a counter of the number of iterations applied to each memory location being programmed by the write command, (c) a timestamp indicating the time of a last applied programming pulse to each memory location being programmed by the write command, and (d) a value of a read resistance of each memory location being programmed by the write command.

23. The method of claim 17 , wherein the iterative write includes a verify step after an application of a programming pulse and wherein the pausing takes effect after the verify step.

24. The method of claim 17 , wherein the executing further comprises storing timing information in response to the completion of the iterative write and wherein a subsequent read operation to the one or more memory locations being programmed by the write command is prevented if the time of the subsequent read operation is less than the timing information.

25. The method of claim 17 , wherein the memory locations are subject to a resistance drift process and wherein the executing further comprises causing a pulse to be applied to each of the memory locations being programmed by the write command to restart the resistance drift process in response to receiving the resume command.