IP Library Granted Patent US 7,820,528
Granted Patent B2
US 7,820,528 · App. 12/535,475 · Granted Oct 26, 2010

Method of forming a leaded molded array package

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Quick Facts
Patent No.
US 7,820,528
App. No.
12/535,475
Granted
Oct 26, 2010
Kind
B2
Abstract

In one embodiment, a method for forming a leaded molded array package includes placing a lead frame assembly into a molding apparatus having lead cavities. The method further includes forming seals between conductive leads within the lead frame assembly and the lead cavities, and encapsulating the lead frame assembly to form a molded array assembly. The molded array assembly is then separated into individual leaded molded packages.

Claims (23)

1. A method for forming leaded molded packages comprising the steps of:

placing a lead frame assembly having conductive leads, flag portions with electronic chips attached thereto and electrically coupled to the conductive leads into a molding apparatus having a plurality of lead channels shaped to prevent flow of encapsulating material between adjacent conductive leads, wherein the lead frame assembly is free of dam-bars;

crimping the conductive leads within the lead channels;

molding portions of the lead frame assembly with an encapsulating layer while leaving portions of the conductive leads exposed to form a molded lead frame assembly; and

singulating the molded lead frame assembly into individual leaded molded packages wherein the step of crimping includes the steps of:

placing the conductive leads into the lead channels having tapered portions with widths less than widths of the conductive leads; and

closing the molding apparatus to force the conductive leads into the tapered portions thereby forming seals between the conductive leads and the lead channels.

2. The method of claim 1 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having electronic chips electrically coupled to the conductive leads with conductive straps.

3. The method of claim 1 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having electronic chips electrically coupled to the conductive leads with conductive straps and wire bonds.

4. The method of claim 1 , wherein the step of providing the lead frame assembly includes providing a lead frame assembly having conductive leads on all sides of at least one electronic chip.

5. The method of claim 1 , wherein the step of singulating includes separating the molded lead frame assembly through portions of the encapsulating layer and the flag portions and separating through the conductive leads.

6. The method of claim 5 , wherein the step of separating the molded lead frame assembly through portions of the encapsulating layer and the flag portions includes separating in a first direction, and wherein the step of separating through the conductive leads includes separating through the conductive leads in a second direction substantially perpendicular to the first direction.

7. The method of claim 1 , wherein the step of providing the lead frame assembly includes providing the lead frame assembly, wherein the flag portions and the conductive leads are substantially co-planar.

8. The method of claim 1 , wherein the step of providing the lead frame assembly includes providing the lead frame assembly wherein the flag portions are offset a distance from the conductive leads.

9. The method of claim 1 , wherein the step of placing the lead frame assembly into the molding apparatus includes placing the lead frame assembly into a molding apparatus having a bottom mold die with a cavity and the plurality of lead channels, wherein the placing step further includes placing the lead frame assembly into the bottom mold die so that the electronic chips are within the cavity of the bottom mold die.

10. The method of claim 1 , wherein the step of placing the lead frame assembly into the molding apparatus includes placing the lead frame assembly into a molding apparatus having a bottom mold die having a single bottom cavity and a mold plate having a mold cavity and the plurality of lead channels, and wherein the placing step further includes placing the lead frame assembly so that an electronic chip is within the mold cavity.

11. The method of claim 10 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having conductive leads on all sides of the electronic chip.

12. The method of claim 1 , further comprising the step of forming the conductive leads to provide a desired shape.

13. The method of claim 1 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having electronic chips of different sizes.

14. The method of claim 1 , wherein the step of molding includes molding portions of the lead frame assembly while leaving surfaces of the flag portions exposed through the encapsulating layer.

15. The method of claim 1 , wherein the step of molding includes molding portions of the lead frame assembly so that the encapsulating layer covers surfaces of the flag portions opposite to the electronic chips.

16. The method of claim 1 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having rails running substantially perpendicular to and integral with the flag portions.

17. The method of claim 16 , wherein the step of placing the lead frame assembly includes placing a lead frame assembly having lead support structures including the conductive leads, and wherein the conductive leads are substantially perpendicular to the flag portions.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →