Level shifter with output latch
A level shifter for a microcontroller shifts an input voltage in a first power domain to an output voltage level consistent with a second power domain. The level shifter is enabled to shift the voltages when both power domains are operative.
1. A device comprising:
a power input to couple to a first power voltage of a first power domain;
a power output to couple to a second power voltage of a second power domain;
an input to receive a logic signal having a first level consistent with the first power domain;
an output to provide a level-shifted logic signal output having a second level consistent with the second power domain;
a voltage detection circuit coupled to the second power domain;
a latch operable to selectively latch, in response to receiving an enable signal received from the voltage detection circuit, the level-shifted logic signal output such that, in response to a change in the enable signal from a first value to a second value, the level-shifted logic signal output that exists just prior to or at a time the enable signal changes to the second value is held at the output while the enable signal has the second value; and
the voltage detection circuit operable to:
determine whether the first power domain is powered; and
provide the enable signal based at least on the determination, wherein the first and second power domains are independent from each other.
2. The device of claim 1 wherein the latch comprises a cross-coupled inverter.
3. The device of claim 1 and further comprising a latch switch coupled to the latch and operable to receive the enable signal that controls the latch switch to latch the level shifted logic signal and stops the latch from drawing current from the second power voltage.
4. The device of claim 3 wherein the latch switch comprises a pair of transistors having gates that couple to the enable signal.
5. The device of claim 4 wherein the cross-coupled inverter comprises two pairs of transistors, each transistor in each pair having gates tied together and having the pairs of gates coupled between the transistors of the other pair of transistors.
6. The device of claim 5 wherein the transistors of the latch switch have outputs that are respectively coupled to one of gates of the pairs of transistors of the cross-coupled inverter.
7. The device of claim 1 wherein the device is coupled between a microcontroller and an input pin of the microcontroller.
8. The device of claim 7 wherein the microcontroller is a controller for a touchscreen and the input pin is to couple to an analog to digital converter of the touchscreen.
9. The device of claim 1 wherein the first power domain is an analog domain and the second power domain is a digital domain.
10. The device of claim 9 wherein the voltage of the analog domain is higher than the voltage of the digital domain.
11. A controller comprising:
a processor operating in a digital power domain, the processor to generate control signals and receive input signals from a touchscreen operating in an analog domain via a plurality of I/O pins;
each input signal I/O pin having at least one level shifter to switch the voltage level of the input signals from the analog domain to the digital domain, each level shifter comprising:
a power input to couple to a first power voltage of a first power domain;
a power output to couple to a second power voltage of a second power domain independent from the first power domain;
an input to receive a logic signal having a first level consistent with the first power domain;
an output to provide a level-shifted logic signal output having a second level consistent with the second power domain; and
a latch operable to selectively latch, in response to receiving an enable signal received from the voltage detection circuit, the level shifted logic signal output such that, in response to a change in the enable signal from a first value to a second value, the level-shifted logic signal output that exists just prior to or at a time the enable signal changes to the second value is held at the output while the enable signal has the second value.
12. The controller of claim 11 wherein the latch comprises a cross-coupled inverter.
13. The controller of claim 11 and further comprising a latch switch coupled to the latch and operable to receive an enable signal that controls the latch switch to latch the level shifted logic signal and stop the latch from drawing current from the second power voltage.
14. The controller of claim 13 wherein the latch switch comprises a pair of transistors having gates that couple to the enable signal input.
15. The controller of claim 14 wherein the cross-coupled inverter comprises two pairs of transistors, each transistor in each pair having gates tied together and having the pairs of gates coupled between the transistors of the other pair.
16. The controller of claim 11 wherein each output signal I/O pin has at least one level shifter to switch the voltage level of input signals from the digital domain to the analog domain.
17. The controller of claim 11 and further comprising a voltage detection circuit coupled to second power domain to determine whether the first power domain is powered and to provide the enable signal as a function of the determination.
18. A method comprising:
shifting input voltages from a first power domain to a second power domain via a level shifter having an input corresponding to first voltages in the first power domain and an output having an output corresponding to second voltages in the second power domain;
detecting that one of the first and second power domains is off via a voltage detection circuit;
latching, via an enable signal received from the voltage detection circuit, an output of the level shifter such that, in response to a change in the enable signal from a first value to a second value, the output of the level shifter that exists just prior to or at a time the enable signal changes to the second value is held at the output while the enable signal has the second value; and
disabling the level shifter responsive to detecting that one of the first and second power domains is off.
19. The method of claim 18 and further comprising:
transferring information from the first power domain to the second power domain and saving the information in the second power domain.