IP Library Granted Patent US 7,999,714
Granted Patent B2
US 7,999,714 · App. 12/542,520 · Granted Aug 16, 2011

Controlling bias current for an analog to digital converter

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Quick Facts
Patent No.
US 7,999,714
App. No.
12/542,520
Granted
Aug 16, 2011
Kind
B2
Abstract

A converter includes an analog to digital converter having a bias current input, a control input, and an analog input to provide a digital output as a function of the analog input. A bias module is coupled to the bias current input to provide bias current to the analog to digital converter. A controller is coupled to the bias module and to the control input of the analog to digital converter. The controller controls the analog to digital converter to sample an analog input and controls the bias module to provide an operating bias current during sampling of the analog input and an idle bias current when not sampling the analog input.

Claims (36)

1. A converter comprising:

an analog-to-digital converter (ADC) configured to receive a bias-current input, a control input, and an analog input and to provide a digital output as a function of the analog input;

a bias module coupled to the ADC and configured to provide the bias-current input to the (ADC); and

a controller coupled to the bias module and to the ADC, the controller being configured to:

control the ADC to sample the analog input; and

control the bias module to provide to the ADC:

an operating bias current as the bias-current input when the ADC is sampling the analog input; and

an idle bias current as the bias-current input when the ADC is not sampling the analog input.

2. The converter of claim 1 , wherein the controller is configured to control the bias module to provide the operating bias current when the controller receives notification that a conversion is to start.

3. The converter of claim 2 , wherein the controller is configured to monitor the conversion and to control the bias module to provide the idle bias current when the conversion is completed.

4. The converter of claim 2 , wherein the ADC consumes current when provided the idle bias current at a current-consumption rate of approximately 25% of its current consumption when provided the operating bias current.

5. The converter of claim 1 , wherein the idle bias current is minimally sufficient to enable the ADC to run.

6. A controller comprising:

a module configured to receive a notification of a conversion of an analog signal to a digital signal;

a module configured to control a bias-current circuit to increase bias current to an analog-to-digital converter (ADC) from an idle bias current to an operating bias current and to control the ADC to start sampling the analog signal; and

a module configured to monitor the conversion and, when the conversion is completed, control the bias-current circuit to decrease bias current from the operating bias current to the idle bias current and to control the ADC to stop sampling the analog signal.

7. The controller of claim 6 , wherein the ADC remains operational during the increase in the bias current without substantially delaying the conversion of the analog signal to the digital signal.

8. The controller of claim 7 , wherein the ADC consumes current when provided the idle bias current at a current-consumption rate of approximately 25% of its current consumption when provided an operating bias current.

9. A system comprising:

plurality of analog-to-digital converters (ADCs) that are each configured to receive at least one of a plurality of analog inputs, a bias-current input, and a control input to provide a digital output as a function of its at least one of the analog inputs;

a bias module coupled to the ADCs and configured to provide the bias-current inputs to the ADCs; and

a controller coupled to the bias module and to the ADCs, the controller being configured to:

control the ADCs to sample at least some of the analog inputs; and

control the bias module to provide each of the ADCs:

an operating bias current as a bias-input current when the ADC is sampling one or more of its at least one of the analog inputs; and

an idle bias current as its bias-input current when the ADC is not sampling one or more of its at least one of the analog inputs.

10. The system of claim 9 , wherein the controller is configured to control the bias module to provide the operating bias current to the ADC when the controller receives notification that a conversion by the ADC is to start.

11. The system of claim 10 , wherein the controller is configured to monitor the conversion and to control the bias module to provide the idle bias current when the conversion is completed.

12. The system of claim 10 , wherein each of the ADCs consumes current when provided an idle bias current at a current-consumption rate of approximately 25% of current consumption when provided an operating bias current.

13. The system of claim 9 , wherein the idle bias current is minimally sufficient to enable the ADC to run.

14. A method comprising:

receiving a notification of a conversion of an analog signal to a digital signal;

controlling a bias-current module to increase bias current to an analog-to-digital converter (ADC) from an idle bias current to an operating bias current and to control the ADC to start sampling the analog signal; and

when the conversion is completed, controlling the bias current module to decrease the bias current from the operating bias current to the idle bias current and to control the ADC to stop sampling the analog signal.

15. The method of claim 14 , wherein the ADC remains operational during the increase in the bias current without delaying the conversion of the analog signal to the digital signal.

16. The method of claim 14 , wherein the ADC consumes current when provided the idle bias current at a current-consumption rate of approximately 25% of current consumption when provided the operating bias current.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2009
From: PEDERSEN, TROND JARLE; FREDRIKSEN, EINAR
To: ATMEL CORPORATION
Reel/Frame 023222/0976 →