Device and method for scanning multiple ADC channels
View Patent ↗An analog to digital converter has an input for coupling to multiple channels having analog signals. The analog to digital converter converts the analog signals on such channels to provide a digital output. A memory device has an enable bit for each of the multiple channels and a current channel register. An interface coupled to the memory device and current channel register selects a next channel for converting by the analog to digital converter, skipping channels that are not enabled.
1. A device comprising:
an analog to digital converter having an input for coupling to multiple channels having analog signals thereon and converting analog signals on such channels to provide a digital output;
a memory device having an enable bit for each of the multiple channels;
a current channel register; and
an interface coupled to the memory device and current channel register to select a next channel for converting by the analog to digital converter, wherein:
the memory device enable bits identify enabled channels in a conversion sequence,
the interface selects a first enabled channel in a next conversion sequence when a last enabled channel in the conversion sequence is converted,
the interface waits for triggering of the next conversion sequence when the last enabled channel in the conversion sequence is converted, and
the analog to digital converter is placed in a lower power consumption mode while waiting for triggering of the next conversion sequence following conversion of the last enabled channel in the conversion sequence.
2. The device of claim 1 wherein the interface skips channels that are not enabled such that only enabled channels are converted in sequence.
3. A system comprising:
an analog to digital converter having an input for coupling to multiple analog signal channels and converting the analog signals on the multiple channels to provide a digital output;
a memory device having an enable bit for each of the multiple channels;
a current channel register;
an interface coupled to the memory device and current channel register to select a next channel for converting by the analog to digital converter; and
a controller to control the analog device and to provide enable bits corresponding to enabled channels to the memory device wherein the controller places the analog to digital converter in a low power state following conversion of the last channel until a new conversion sequence is triggered.
4. The system of claim 3 wherein the interface selects the next enabled channel as a function of the enable bits in the memory device.
5. The system of claim 3 wherein the controller provides enable bits corresponding to a next conversion sequence when it triggers the analog device to provide analog signals on selected channels.
6. A method comprising:
setting enable bits in a channel enable register corresponding to enabled channels of a plurality of channels, some of which are not enabled;
setting a current channel register to identify a current channel being converted;
sequentially converting analog signals on the enabled channels as a function of the enable bits in the channel enable register and the current channel register while skipping conversion of non-enabled channels, wherein the enable bits are set corresponding to a current channel conversion sequence, and a first enabled channel in a next channel conversion sequence is converted when a last enabled channel in the current channel conversion sequence is converted;
waiting for the next channel conversion sequence to be triggered when the last enabled channel in the current channel conversion sequence is converted; and
placing the analog to digital converter in a lower power consumption mode while waiting for triggering of the next channel conversion sequence following conversion of the last enabled channel in the current channel conversion sequence.
7. The method of claim 6 wherein channels that are not enabled are skipped such that only enabled channels are converted in a channel conversion sequence.