IP Library Granted Patent US 7,901,990
Granted Patent B2
US 7,901,990 · App. 12/553,706 · Granted Mar 8, 2011

Method of forming a molded array package device having an exposed tab and structure

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Quick Facts
Patent No.
US 7,901,990
App. No.
12/553,706
Granted
Mar 8, 2011
Kind
B2
Abstract

In one embodiment, a method for forming a molded flat pack style package includes attaching electronic chips to an array lead frame, which includes a plurality of elongated flag portions with tab portions and a plurality of leads. The method further includes connecting the electronic chips to specific leads, and then molding the array lead frame while leaving portions of the leads exposed to form a molded array structure. The molded array structure is then separated to provide molded flat pack style packages having exposed leads for insertion mount and exposed tab portions. In an alternative embodiment, the separation step produces a no-lead configuration with exposed tab portions.

Claims (35)

1. A method for forming molded array package devices comprising the steps of:

providing a main lead frame having a plurality of flags with tab portions and a plurality of leads in spaced relationship with the plurality of flags;

mounting electronic chips to the plurality of flags;

coupling the electronic chips to the plurality of leads;

encapsulating the main lead frame wherein an encapsulation layer covers all of the electronic chips mounted to the plurality of flags, and wherein the encapsulation layer runs continuously between each adjacent flag adjacent to the electronic chips while leaving portions of the plurality of leads exposed to provide a molded array package assembly; and

separating the molded array package assembly into separate molded array package devices by separating the molded array package assembly through the encapsulation layer between at least two adjacent flags adjacent to the electronic chips, wherein the step of separating includes cutting through the plurality of flag portions, and wherein the step of separating includes separating through the plurality of leads to form leadless molded array packages.

2. A process for forming a flat pack structure comprising the steps of:

providing an array lead frame having a plurality of elongated flag portions with tabs and a plurality of leads;

attaching electronic chips to the elongated flag portions;

coupling the electronic chips to the plurality of leads;

forming a continuous encapsulating layer over portions of the elongated flags portions while leaving the tabs and portions of the plurality of leads exposed to provide a molded assembly; and

singulating the molded assembly into separate packages by separating through the plurality of elongated flag portions, through the continuous encapsulating layer between one elongated flag portion and an adjacent elongated flag portion in a first direction, and through the plurality of leads in a second direction substantially perpendicular to the first direction to provide flat pack structures with exposed tab portions and with a no-lead configuration.

3. A multi-chip packaged device comprising:

a first flag having a tab portion

a first electronic chip attached to the first flag;

a first plurality of conductive leads in spaced relationship with the first flag, wherein the first electronic chip is coupled to at least a portion of the first plurality of conductive leads;

a second flag in spaced relationship with the first plurality of conductive leads;

a second plurality of conductive leads in spaced relationship with the second flag;

a second electronic chip attached to the second flag and coupled to the first and second plurality of conductive leads, wherein the second electronic chip provides a function different from the first electronic chip;

a first encapsulating layer covering the first flag, the first electronic chip and portions of the first conductive leads to form a first packaged device; and

a second encapsulating layer covering the second flag, the second electronic chip, and other portions of the first conductive leads to form a second flat packaged device, wherein remaining portions of the first conductive leads are exposed between the first and second packaged devices, and wherein at least one of the first plurality of conductive leads connects the first and second packaged devices together.

4. The device of claim 3 , wherein the tab portion is exposed for attaching to a next level of assembly.

5. The device of claim 3 , wherein the second plurality of conductive leads are exposed and extend outwardly from the second flat package device.

6. The device of claim 3 , wherein the second plurality of conductive leads are configured as leadless connective portions.

7. A process for forming a multi-chip molded structure comprising the steps of:

providing an array lead frame having a plurality of first flag portions with tab portions, a plurality of second flag portions without tab portions, and a plurality of leads, wherein the plurality of leads includes conductive leads that extend between the plurality of first flag portions and the plurality of second flag portions;

attaching electronic components to the plurality of first flag portions and the plurality of second flag portions;

coupling the electronic components to the plurality of leads;

forming a first continuous encapsulating layer overlying portions of the plurality of first flag portions while leaving the tab portions exposed;

forming a second continuous encapsulating layer overlying portions of the plurality of second flag portions; and

singulating through the first and second continuous encapsulating layers in a first direction to provide a first molded device portion connected to a second molded device portion by the conductive leads.

8. The method of claim 7 , wherein the step of providing the array lead frame includes providing the array lead frame, wherein at least a portion of the plurality of first flag portions include tab portions, and wherein the step of forming the first continuous encapsulating layer includes forming the first continuous encapsulating layer, wherein at least one tab portion is exposed.

9. The method of claim 7 , wherein the step of singulating includes singulating through the first and second continuous encapsulating layers to provide a first molded device that includes more than one first flag portion.

10. The method of claim 7 , wherein the step of singulating includes singulating through the first and second continuous encapsulating layers to provide a second molded device that includes more than one second flag portion.

11. The method of claim 7 , wherein the step of singulating includes singulating in a second direction so that the second molded device includes leadless connective portions on one side.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038631/0345 →
RELEASE OF SECURITY INTEREST Recorded May 6, 2016
From: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038632/0074 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
SECURITY AGREEMENT Recorded Jan 19, 2010
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 023826/0725 →