Adaptive regulator for idle state in a charge pump circuit of a memory device
View Patent ↗An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
1. An apparatus comprising:
a charge pump;
a regulator device coupled to the charge pump and a target node to provide a first voltage level to the target node;
a first comparator coupled to the target node; and
a first transistor to respond to an output of the first comparator to maintain the target node at a second voltage level during switching between a first operation and a second operation in at least one memory element coupled to the target node, wherein the first operation includes a modify operation and the second operation includes a read operation.
2. The apparatus of claim 1 , wherein the first transistor includes a first node coupled to the target node, a second node coupled to the charge pump, and a gate coupled to an output of the first comparator.
3. The apparatus of claim 1 further comprising a second comparator coupled to the target node and the first comparator to maintain the target node within a voltage range during switching between the modify operation and the read operation.
4. The apparatus of claim 3 , wherein the second comparator includes a first input coupled to the target node, a second input coupled to a reference voltage, and an output to affect a voltage at the target node.
5. The apparatus of claim 1 , wherein the regulator device includes a linear regulator device.
6. The apparatus of claim 1 , wherein the first comparator includes a first input coupled to the target node, a second input coupled to a reference voltage, and an output coupled to a gate of the first transistor.
7. The apparatus of claim 6 , wherein the first transistor includes a p-channel metal-oxide semiconductor transistor (PMOS) transistor.
8. An apparatus comprising:
a charge pump;
a regulator device coupled to the charge pump and a target node to provide a first voltage level to the target node;
a first comparator coupled to the target node;
a first transistor to respond to an output of the first comparator to maintain the target node at a second voltage level during switching between a first operation and a second operation in at least one memory element coupled to the target node; and
a second transistor coupled between the target node and a ground potential, the second transistor including a gate controlled by a second comparator.
9. The apparatus of claim 8 , wherein the second comparator includes a first input coupled to the target node, a second input coupled to a reference voltage, and an output coupled to the gate of the second transistor.