Method and apparatus for dithering in multi-bit sigma-delta digital-to-analog converters
A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M−N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
1. An apparatus for reduction of unwanted idle tones by dithering a digital signal in a multi-bit (M-bit, M>1) sigma-delta digital-to-analog converter (DAC), comprising:
a sigma-delta multi-bit modulator having a digital signal input and a plurality of variable resolution outputs, the sigma-delta multi-bit modulator comprising:
a digital loop filter,
a plurality of random sequence generators, and
a plurality of variable resolution quantizers,
wherein
the digital loop filter receives a digital signal at the digital signal input and converts the digital signal to L-bit digital words,
each of the plurality of random sequence generators creates a plurality of random numbers N(n) in a sequence, where N(n) are random integer numbers between 1 and M, and
each of the plurality of variable resolution quantizers reduces the L-bit digital words to N(n)-bit digital words and then adds zeros to the N(n)-bit digital words to form M-bit digital words, where M is greater than N(n) and M-N(n) least significant bits of the M-bit digital words are zeros;
a plurality of multi-bit digital-to-analog converters (DACs), each of the plurality of multi-bit DACs having an analog output and a digital input coupled to a respective one of the plurality of variable resolution outputs from the sigma-delta multi-bit modulator; and
an analog low pass filter having a plurality of analog inputs coupled to respective outputs of the plurality of multi-bit DACs.
2. The apparatus according to claim 1 , wherein each of the outputs of the plurality of variable resolution quantizers has a different number of bits then the others.
3. The apparatus according to claim 1 , wherein the outputs of the plurality of variable resolution quantizers have the same number of bits.
4. The apparatus according to claim 1 , wherein one of the plurality of variable resolution quantizers has a three bit output and another one of the plurality of variable resolution quantizers has a four bit output.
5. The apparatus according to claim 1 , wherein each of the plurality of random sequence generators comprises:
a linear feedback shift register (LFSR) having an R-bit output;
a plurality of digital comparators, each of the plurality of digital comparators having a different digital threshold, an R-bit digital input coupled to the LFSR, and a digital output; and
a digital adder having inputs coupled to the digital outputs of the plurality of digital comparators, and an output coupled to the variable resolution quantizer.
6. The apparatus according to claim 5 , wherein the LFSR is a Galois LFSR.
7. The apparatus according to claim 1 , wherein each of the plurality of variable resolution quantizers comprises:
an N-bit truncator having an L-bit input, an N(n)-bit input and an N(n)-bit output, wherein the L-bit input is coupled to the digital loop filter for receiving the L-bit digital words and the N-bit input is coupled to the random sequence generator; and
a zeros padding function coupled to the N(n)-bit output of the N-bit truncator, wherein the zeros padding function adds zeros to M-N(n) least significant bits of the M-bit digital words.
8. The apparatus according to claim 1 , wherein each of the plurality of variable resolution quantizers comprises:
an N-bit rounder having an L-bit input, an N(n)-bit input and an N(n)-bit output, wherein the L-bit input is coupled to the digital loop filter for receiving the L-bit digital words and the N-bit input is coupled to the random sequence generator; and
a zeros padding function coupled to the N(n)-bit output of the N-bit rounder, wherein the zeros padding function adds zeros to M-N(n) least significant bits of the M-bit digital words.
9. The apparatus according to claim 1 , wherein sampling of the L-bit digital words and generation of respective ones of the random number sequences N(n) occur at substantially the same times.
10. The apparatus according to claim 1 , wherein sampling of the L-bit digital words and generation of respective ones of the random number sequences N(n) occur at frequency fs intervals.