IP Library Granted Patent US 8,390,110
Granted Patent B2
US 8,390,110 · App. 12/582,582 · Granted Mar 5, 2013

Integrated circuit packaging system with cavity and method of manufacture thereof

Inventors: Sang-Ho Lee (Yeoju, KR); Taewoo Lee (Icheon-Si, KR); Soo-San Park (Seoul, KR)
Assignee: STATS ChipPAC Ltd.
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Quick Facts
Patent No.
US 8,390,110
App. No.
12/582,582
Granted
Mar 5, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: mounting a substrate-less integrated circuit package, having a terminal having characteristics of an intermetallic compound, over a substrate; connecting the substrate and the substrate-less integrated circuit package; and forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed.

Claims (34)

1. A method of manufacture of an integrated circuit packaging system comprising:

mounting a substrate-less integrated circuit package, having an internal adhesive layer and a terminal having characteristics of an intermetallic compound, over a substrate;

connecting the substrate and the substrate-less integrated circuit package; and

forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed, the base encapsulation having a cavity exposing the internal adhesive layer.

2. The method as claimed in claim 1 further comprising forming the substrate-less integrated circuit package having the terminal having characteristics of the intermetallic compound includes:

connecting a module interconnect and a conductive layer resulting in the intermetallic compound layer at the attachment site; and

forming the terminal by removing the conductive layer and exposing the intermetallic compound of the terminal.

3. The method as claimed in claim 1 further comprising forming the substrate-less integrated circuit package includes forming a module encapsulation substantially coplanar with the terminal.

4. The method as claimed in claim 1 further comprising forming the substrate-less integrated circuit package includes forming a module encapsulation having a taper edge.

5. The method as claimed in claim 1 wherein forming the base encapsulation includes forming the base encapsulation having the cavity exposing a portion of the substrate-less integrated circuit package.

6. A method of manufacture of an integrated circuit packaging system comprising:

mounting a base device over a substrate;

mounting a substrate-less integrated circuit package, with an internal adhesive layer and a terminal having characteristics of an intermetallic compound, over the base device;

connecting a package interconnect to the substrate and the substrate-less integrated circuit package; and

forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed, the base encapsulation having a cavity exposing the internal adhesive layer.

7. The method as claimed in claim 6 further comprising forming the substrate-less integrated circuit package includes forming the terminal in a multi-row configuration, the terminal exposed from the base encapsulation.

8. The method as claimed in claim 6 further comprising forming the substrate-less integrated circuit package includes forming a module encapsulation substantially coplanar with the internal adhesive layer and the terminal.

9. The method as claimed in claim 6 further comprising forming the substrate-less integrated circuit package includes forming a substrate-less Internal Stacking Module having a module encapsulation with a taper edge.

10. The method as claimed in claim 6 wherein forming the base encapsulation includes forming the base encapsulation having the cavity with a portion of the substrate-less integrated circuit package exposed therein.

11. An integrated circuit packaging system comprising:

a substrate;

a substrate-less integrated circuit package, having an internal adhesive layer and a terminal having characteristics of an intermetallic compound, over and connected to the substrate; and

a base encapsulation over the substrate-less integrated circuit package with the terminal exposed, the base encapsulation having a cavity exposing the internal adhesive layer.

12. The system as claimed in claim 11 wherein the substrate-less integrated circuit package includes the terminal in a multi-row configuration.

13. The system as claimed in claim 11 wherein the substrate-less integrated circuit package includes a module encapsulation substantially coplanar with the terminal.

14. The system as claimed in claim 11 wherein the substrate-less integrated circuit package includes a module encapsulation having a taper edge.

15. The system as claimed in claim 11 wherein the base encapsulation includes the base encapsulation having the cavity exposing a portion of the substrate-less integrated circuit package.

16. The system as claimed in claim 11 further comprising:

a base device over the substrate; and

a package interconnect connected to the substrate and the substrate-less integrated circuit package.

17. The system as claimed in claim 16 wherein the substrate-less integrated circuit package includes the terminal in a multi-row configuration, the terminal exposed from the base encapsulation.

18. The system as claimed in claim 16 wherein the substrate-less integrated circuit package includes a module encapsulation substantially coplanar with a portion of the internal adhesive layer and the terminal.

19. The system as claimed in claim 16 wherein the substrate-less integrated circuit package includes a substrate-less Internal Stacking Module having a module encapsulation with a taper edge.

20. The system as claimed in claim 16 wherein the base encapsulation includes the base encapsulation having the cavity with a portion of the substrate-less integrated circuit package exposed therein.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2009
From: LEE, SANG-HO; LEE, TAEWOO; PARK, SOO-SAN
To: STATS CHIPPAC LTD.
Reel/Frame 023452/0749 →
Continuity (1)
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