Nonvolatile memory cell comprising a nanowire and manufacturing method thereof
View Patent ↗A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.
1. A memory cell, the memory cell comprising:
a substrate;
a nanowire extending along a vertical trench formed in the substrate;
a control gate surrounding at least a part of the nanowire and configured and arranged to control a conductance state of a portion of the nanowire for storing data in the memory cell;
a charge storage structure arranged between the control gate and the nanowire and configured and arranged to store the data as an electrical charge; and
an access gate configured and arranged to control a conductance state of another portion of the nanowire to electrically couple the nanowire to an access circuit for accessing, by reading or writing, the data via the charge storage structure.
2. The memory cell according to claim 1 , comprising a first source/drain region coupled to a substrate external end portion of the nanowire and comprising a second source/drain region coupled to a substrate internal end portion of the nanowire.
3. The memory cell according to claim 2 , comprising a contact structure coupled to the first source/drain region.
4. The memory cell according to claim 2 , comprising an electrically insulating spacer structure surrounding the first source/drain region for electrically decoupling the first source/drain region from the control gate.
5. The memory cell according to claim 3 , wherein the contact structure has a larger dimension than the first source/drain region in a direction being perpendicular to the vertical extension of the trench.
6. The memory cell according to claim 1 , wherein the charge storage structure comprises one of the group consisting of a floating gate, a silicon oxide-silicon nitride-silicon oxide layer sequence, a silicon nitride structure, and a nano-crystal dot structure.
7. The memory cell according to claim 1 , wherein the control gate surrounds the nanowire along the entire circumference of the nanowire.
8. The memory cell according to claim 1 , wherein the nanowire has a diameter of less than 100 nm, particularly of less than 50 nm, more particularly of less than 20 nm, in a direction perpendicular to the vertical extension of the trench.
9. The memory cell according to claim 1 , wherein the access gate surrounds the nanowire along the entire circumference of the nanowire.
10. The memory cell according to claim 9 , wherein the access gate is arranged deeper within the trench than the control gate.
11. The memory cell according to claim 1 , wherein the nanowire includes one of the group consisting of a semiconductor nanowire, a carbon nanotube, a silicon nanowire, and a group III-group V nanowire.
12. The memory cell according to claim 1 , adapted as a flash memory cell.
13. The memory cell according to claim 1 , adapted as a multi-bit memory cell.
14. A memory array, the memory array comprising a plurality of memory cells according to claim 1 formed in the substrate.
15. The memory array according to claim 14 , comprising electrically insulating regions between adjacent trenches.
16. The memory array according to claim 14 , wherein a common control gate is provided in common for a sub-group of at least two of the plurality of memory cells.
17. A method of manufacturing a memory cell, the method comprising
forming a vertical trench in a substrate;
forming a nanowire extending along the vertical trench;
forming a control gate surrounding at least a part of the nanowire and configured and arranged to control a conductance state of a portion of the nanowire for storing data in the memory cell;
arranging a charge storage structure between the control gate and the nanowire, the charge storage structure configured and arranged to store the data as an electrical charge; and
forming an access gate configured and arranged to control a conductance state of another portion of the nanowire to electrically couple the nanowire to an access circuit for accessing the data via the charge storage structure.
18. The method according to claim 17 , wherein the nanowire is formed by one of the group consisting of a growing procedure and an etching procedure.