Interdigitated capacitors
View Patent ↗The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.
1. A capacitor pair device comprising:
a substrate; and
a plurality of runners on the substrate, the plurality of runners forming:
a first plate of a first capacitor;
a second plate of the first capacitor;
a first plate of a second capacitor; and
a second plate of the second capacitor, wherein a cross section of the device in a plane normal to the substrate comprises runners arranged in a row in the following sequence:
c-i-a-i-c-i-b-i-c-i-a-i-c-i-b-i-c where:
i designates insulating material;
a designates a runner that comprises the first plate of the first capacitor;
b designates a runner that comprises the first plate of the second capacitor; and
c designates a runner that comprises the second plate of the first capacitor and the second plate of the second capacitor.
2. The device of claim 1 wherein the capacitor pair device comprises an integrated circuit.
3. A capacitor pair device comprising:
a substrate; and
a plurality of runners on the substrate, the plurality of runners forming:
a first plate of a first capacitor;
a second plate of the first capacitor;
a first plate of a second capacitor; and
a second plate of the second capacitor, wherein a cross section of the device in a plane normal to the substrate comprises runners arranged in a row in the following sequence:
c 1 -i-a-i-c 1 -i-c 2 -i-b-i-c 2 -i-c 1 -i-a-i-c 1 -i-c 2 -i-b-i-c 2 where:
i designates insulating material;
a designates a runner that comprises the first plate of the first capacitor;
b designates a runner that comprises the first plate of the second capacitor;
c 1 designates a runner that comprises the second plate of the first capacitor; and
c 2 designates a runner that comprises the second plate of the second capacitor.
4. The device of claim 3 wherein the capacitor pair device comprises an integrated circuit.
5. A capacitor pair device comprising:
a substrate; and
a plurality of runners on the substrate, the plurality of runners forming:
a first plate of a first capacitor;
a second plate of the first capacitor;
a first plate of a second capacitor; and
a second plate of the second capacitor, wherein a cross section of the device in a plane normal to the substrate comprises runners arranged in a row, in the following sequence:
c 1 -i-a-i-c 1 -i-g-i-c 2 -i-b-i-c 2 -i-g-i-c 1 -i-a-i-c 1 -i-g-i-c 2 where:
i designates insulating material;
a designates a runner that comprises the first plate of the first capacitor;
b designates a runner that comprises the first plate of the second capacitor;
c 1 designates a runner that comprises the second plate of the first capacitor;
c 2 designates a runner that comprises the second plate of the second capacitor; and
g designates a runner that comprises a ground plane.
6. The device of claim 5 wherein the capacitor pair device comprises an integrated circuit.