IP Library Granted Patent US 8,158,510
Granted Patent B2
US 8,158,510 · App. 12/621,738 · Granted Apr 17, 2012

Semiconductor device and method of forming IPD on molded substrate

Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,158,510
App. No.
12/621,738
Granted
Apr 17, 2012
Kind
B2
Abstract

A semiconductor device is made by depositing an encapsulant material between first and second plates of a chase mold to form a molded substrate. A first conductive layer is formed over the molded substrate. A resistive layer is formed over the first conductive layer. A first insulating layer is formed over the resistive layer. A second insulating layer is formed over the first insulating layer, resistive layer, first conductive layer, and molded substrate. A second conductive layer is formed over the first insulating layer, resistive layer, and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. The first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a MIM capacitor. The second conductive layer is wound to exhibit inductive properties.

Claims (83)

1. A method of making a semiconductor device, comprising:

forming a molded substrate;

forming a first conductive layer over the molded substrate;

removing a portion of the first conductive layer;

forming a resistive layer over the first conductive layer;

forming a first insulating layer over the resistive layer;

forming a second insulating layer over the first insulating layer, resistive layer, first conductive layer, and molded substrate;

removing a portion of the second insulating layer to expose the first insulating layer, resistive layer, and first conductive layer;

forming a second conductive layer over the first insulating layer, resistive layer, and first conductive layer;

forming a third insulating layer over the second insulating layer and second conductive layer;

removing a portion of the third insulating layer to expose the second conductive layer; and

forming a bump over the second conductive layer.

2. The method of claim 1 , further including depositing an encapsulant material between first and second plates of a chase mold to form the molded substrate.

3. The method of claim 2 , further including:

applying a first releasable layer over the first plate; and

applying a second releasable layer over the second plate.

4. The method of claim 3 , further including forming a conductive film layer over the first releasable layer to create the first conductive layer and a cavity in the molded substrate.

5. The method of claim 1 , further including forming a third conductive layer between the second conductive layer and bump.

6. The method of claim 1 , wherein the first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.

7. The method of claim 1 , wherein the second conductive layer is wound to exhibit inductive properties.

8. A method of making a semiconductor device, comprising:

forming a molded substrate;

forming a first conductive layer over the molded substrate;

forming a first insulating layer over the first conductive layer;

forming a second insulating layer over the first insulating layer, first conductive layer, and molded substrate;

forming a second conductive layer over the first insulating layer and first conductive layer;

forming a third insulating layer over the second insulating layer and second conductive layer; and

forming an interconnect over the second conductive layer.

9. The method of claim 8 , further including depositing an encapsulant material between first and second plates of a chase mold to form the molded substrate.

10. The method of claim 9 , further including:

applying a first releasable layer over the first plate; and

applying a second releasable layer over the second plate.

11. The method of claim 10 , further including forming a film layer over the first releasable layer to create a cavity in the molded substrate.

12. The method of claim 8 , wherein the interconnect includes a bump or bond wire.

13. The method of claim 8 , wherein the first conductive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor, and the second conductive layer is wound to exhibit inductive properties.

14. A method of making a semiconductor device, comprising:

forming a molded substrate, wherein forming the molded substrate includes depositing an encapsulant material between a first plate of a chase mold and a second plate of the chase mold;

forming an integrated passive device (IPD) over the molded substrate; and

forming an interconnect over the IPD.

15. The method of claim 14 , wherein forming the IPD includes:

forming a first conductive layer over the molded substrate;

forming a resistive layer over the first conductive layer;

forming a first insulating layer over the resistive layer;

forming a second insulating layer over the first insulating layer, resistive layer, first conductive layer, and molded substrate;

forming a second conductive layer over the second insulating layer, resistive layer, and first conductive layer; and

forming a third insulating layer over the second insulating layer and second conductive layer.

16. The method of claim 15 , wherein the first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor, and the second conductive layer is wound to exhibit inductive properties.

17. A method of making a semiconductor device, comprising:

forming a molded substrate;

forming an integrated passive device (IPD) over the molded substrate;

forming an interconnect over the IPD;

depositing an encapsulant material between first and second plates of a chase mold to form the molded substrate;

applying a first releasable layer over the first plate; and

applying a second releasable layer over the second plate.

18. The method of claim 17 further including forming a film layer over the first releasable layer to create a cavity in the molded substrate.

19. A semiconductor device, comprising:

a molded substrate;

a first conductive layer formed over the molded substrate;

a first insulating layer formed over the first conductive layer;

a second insulating layer formed over the first insulating layer, first conductive layer, and molded substrate;

a second conductive layer formed over the second insulating layer and first conductive layer;

a third insulating layer formed over the second insulating layer and second conductive layer; and

an interconnect formed over the second conductive layer.

20. The semiconductor device of claim 19 , wherein the molded substrate includes a cavity formed in a surface of the molded substrate.

21. The semiconductor device of claim 19 , wherein the interconnect includes a bump or bond wire.

22. The semiconductor device of claim 19 , wherein the first conductive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor.

23. The semiconductor device of claim 19 , wherein a portion of the second conductive layer includes an inductor.

24. The semiconductor device of claim 19 , wherein a portion of the second conductive layer includes an integrated passive device.

25. A method of making a semiconductor device, comprising:

applying a first releasable layer over a first plate of a chase mold;

applying a second releasable layer over a second plate of the chase mold;

depositing an encapsulant material between the first plate of the chase mold and the second plate of the chase mold to form a molded substrate;

forming an integrated passive device (IPD) over the molded substrate; and

forming an interconnect over the IPD.

26. The method of claim 25 , further comprising forming a film layer over the first releasable layer.

27. The method of claim 25 , wherein forming the IPD over the molded substrate comprises:

forming a first conductive layer over the molded substrate;

forming a resistive layer over the first conductive layer;

forming a first insulating layer over the resistive layer;

forming a second insulating layer over the first insulating layer, resistive layer, first conductive layer, and molded substrate;

forming a second conductive layer over the second insulating layer, resistive layer, and first conductive layer; and

forming a third insulating layer over the second insulating layer and second conductive layer.

28. The method of claim 27 , wherein the first conductive layer, resistive layer, first insulating layer, and second conductive layer constitute a metal-insulator-metal capacitor, and the second conductive layer is wound to exhibit inductive properties.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY NAME PREVIOUSLY RECORDED AT REEL: 064789 FRAME: 0474 ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 8, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064842/0046 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. (REEL: 38378 FRAME: 0280) Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 064789/0474 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0280 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2009
From: LIN, YAOJIAN
To: STATS CHIPPAC, LTD.
Reel/Frame 023542/0819 →
Continuity (1)
Related Publication 20110115050A1 · May 19, 2011