IP Library Granted Patent US 7,910,425
Granted Patent B2
US 7,910,425 · App. 12/727,304 · Granted Mar 22, 2011

Multiple doping level bipolar junctions transistors and method for forming

Assignee: Agere Systems Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,910,425
App. No.
12/727,304
Granted
Mar 22, 2011
Kind
B2
Abstract

A process for forming bipolar junction transistors having a plurality of different collector doping densities on a semiconductor substrate and an integrated circuit comprising bipolar junction transistors having a plurality of different collector doping densities. A first group of the transistors are formed during formation of a triple well for use in providing triple well isolation for complementary metal oxide semiconductor field effect transistors also formed on the semiconductor substrate. Additional bipolar junction transistors with different collector doping densities are formed during a second doping step after forming a gate stack for the field effect transistors. Implant doping through bipolar transistor emitter windows forms bipolar transistors having different doping densities than the previously formed bipolar transistors. According to one embodiment of the present invention, bipolar junction transistors having six different collector dopant densities (and thus six different breakdown characteristics) are formed.

Claims (26)

1. A process for forming bipolar junction transistors and metal oxide semiconductor field effect transistors over a substrate, the process comprising:

forming a first doped tub and a plurality of doped collector sinker regions within the substrate;

forming a second and a third doped tub within the substrate;

forming a triple well region for cooperating with the second and the third doped tubs to electrically isolate the first doped tub from the substrate and forming a first plurality of subcollector regions comprising a first doping level;

forming structures associated with the metal oxide semiconductor field effect transistor;

doping a first subset of the first plurality of subcollector regions to form a second plurality of subcollector regions while doping other regions of the substrate to form a third plurality of subcollector regions, wherein the second plurality of subcollector regions comprise a second doping level and the third plurality of subcollector regions comprise a third doping level; and

doping a second subset of the first plurality of subcollector regions to form a fourth plurality of subcollector regions while doping a subset of the third plurality of subcollector regions to form a fifth plurality of subcollector regions and while doping a subset of the first subset of the first plurality of subcollector regions to form a sixth plurality of subcollector regions, wherein the fourth plurality of subcollector regions comprise a fourth doping level, and wherein the fifth plurality of subcollector regions comprise a fifth doping level, and wherein the sixth plurality of subcollector regions comprise a sixth doping level.

2. The process of claim 1 further comprising forming a base region and an emitter over the subcollector and doped sinker region in each of the first, second, third, and fourth BJT regions.

3. The process of claim 2 wherein BJT in the first, second, third, and fourth BJT regions exhibit different breakdown characteristics according their respective doping levels.

4. The process of claim 1 wherein forming structures associated with the metal oxide semiconductor field effect transistor further comprises depositing a layer of polysilicon and forming a gate for the metal oxide semiconductor field effect transistor.

5. The process of claim 1 , wherein the subcollectors in the first, second and fourth BJT regions and the triple wells in the first MOSFET region are formed using a first mask.

6. The process of claim 5 , wherein concurrently doping unmasked portions of the doped sinker regions in the first, second, third and fourth BJT regions and the first doped tub regions with the second type dopant includes using a second mask different from the first mask.

7. The process of claim 6 , wherein doping the third and fourth BJT regions with the second dopant type to form a subcollector in the third BJT region and further doping the subcollector in the fourth BJT region includes using a third mask different from the first and second masks.

8. A process for forming bipolar junction transistors in a semiconductor substrate further comprising a metal oxide semiconductor field effect transistor, the process comprising:

forming a first doped tub and a plurality of doped collector sinker regions within the substrate;

forming a second and a third doped tub within the substrate;

forming a triple well region for cooperating with the second and the third doped tubs to electrically isolate the first doped tub from the substrate and forming a first plurality of subcollector regions comprising a first doping level;

forming structures associated with the metal oxide semiconductor field effect transistor;

doping a first subset of the first plurality of subcollector regions to form a second plurality of subcollector regions while doping other regions of the substrate to form a third plurality of subcollector regions, wherein the second plurality of subcollector regions comprise a second doping level and the third plurality of subcollector regions comprise a third doping level; and

doping a second subset of the first plurality of subcollector regions to form a fourth plurality of subcollector regions while doping a subset of the third plurality of subcollector regions to form a fifth plurality of subcollector regions and while doping a subset of the first subset of the first plurality of subcollector regions to form a sixth plurality of subcollector regions, wherein the fourth plurality of subcollector regions comprise a fourth doping level, and wherein the fifth plurality of subcollector regions comprise a fifth doping level, and wherein the sixth plurality of subcollector regions comprise a sixth doping level.

9. The process of claim 8 further comprising forming a base region and an emitter region for cooperating with one of the first, second, third, fourth, fifth and sixth subcollector region and one of the plurality of doped collector sinker regions to form, respectively, a first, second, third, fourth, fifth and sixth bipolar junction transistor.

10. The process of claim 9 wherein the first, second, third, fourth, fifth and sixth bipolar junction transistors exhibit breakdown characteristics in the following order beginning with the bipolar junction transistor having the highest breakdown voltage, according to the doping level of the subcollector, the first doping level, the fourth doping level, the third doping level, the second doping level, the fifth doping level and the sixth doping level.

11. The process of claim 8 wherein the step of forming structures associated with the metal oxide semiconductor field effect transistor further comprises depositing a layer of polysilicon and forming a gate for the metal oxide semiconductor field effect transistor.

12. The process of claim 8 wherein the structures associated with the metal oxide semiconductor field effect transistor comprise a gate structure, and wherein the step of forming structures associated with the metal oxide semiconductor field effect transistor is executed after the step of forming the triple well region and the first plurality of subcollector regions and before the step of doping the first subset of the first plurality of subcollector regions.

13. The process of claim 12 wherein the step of forming structures associated with the metal oxide semiconductor field effect transistor is executed before the step of doping the first subset of the first plurality of subcollector regions.

14. The process of claim 8 further comprising forming material layers overlying the substrate and forming emitter windows within one or more of the material layers, wherein the step of doping the second subset of the first plurality of subcollector regions while doping a subset of the third plurality of subcollector regions and while doping a subset of the first subset of the first plurality of subcollector regions comprises doping through the emitter windows.

Assignments (11)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2010
From: KERR, DANIEL CHARLES; CARROLL, MICHAEL SCOTT; HAMAD, AMAL MA; LAI, THIET THE; KEY, ROGER W.
To: AGERE SYSTEMS INC.
Reel/Frame 024106/0545 →
Continuity (4)
Division 12243137 · Oct 1, 2008
Division 11458270 · Jul 18, 2006
Division 10953894 · Sep 29, 2004
Related Publication 20100173459A1 · Jul 8, 2010