p-FET with a strained nanowire channel and embedded SiGe source and drain stressors
Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.
1. A method of fabricating a field effect transistor (FET), comprising the steps of:
providing a doped substrate having a dielectric thereon;
placing at least one silicon nanowire on the dielectric;
masking off one or more portions of the nanowire leaving other portions of the nanowire exposed;
growing epitaxial germanium on the exposed portions of the nanowire;
interdiffusing the epitaxial germanium with silicon in the nanowire to form silicon germanium regions embedded in the nanowire that introduce compressive strain in the nanowire,
wherein the doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded silicon germanium regions serve as source and drain regions of the FET; and
further increasing a concentration of germanium in the silicon germanium regions using germanium condensation.
2. The method of claim 1 , wherein the doped substrate comprises a p ++ doped silicon substrate.
3. The method of claim 1 , wherein the dielectric comprises a nitride film.
4. The method of claim 1 , wherein the epitaxial germanium is grown on the exposed portions of the nanowire at a temperature of about 300° C. in the presence of a germanium precursor.
5. The method of claim 4 , wherein the germanium precursor comprises germane.
6. The method of claim 1 , wherein the epitaxial germanium is interdiffused with the silicon in the nanowire using thermal mixing.
7. The method of claim 1 , wherein the one or more portions of the nanowire are masked off using a hydrogen silsesquioxane mask.
8. The method of claim 1 , further comprising the step of:
doping the silicon germanium regions using one of in-situ doping and ion-implantation.
9. A method of fabricating a FET, comprising the steps of:
providing a silicon-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX);
forming a plurality of nanowires and pads in the SOI layer with the pads attached at opposite ends of the nanowires in a ladder-like configuration;
forming a thermal oxide over the nanowires and pads;
forming a dummy gate on the thermal oxide surrounding at least a portion of each of the nanowires;
removing the thermal oxide from portions of the nanowires extending out from the gate and from at least a portion of each of the pads;
growing epitaxial germanium on the portions of the nanowires extending out from the gate and the portion of the pads from which the thermal oxide is removed;
interdiffusing the epitaxial germanium with silicon in the nanowires and pads to form embedded silicon germanium source and drain regions that introduce compressive strain in the nanowires;
depositing a dielectric film over the dummy gate and embedded silicon germanium source and drain regions;
removing the dummy gate to introduce additional strain in the nanowires; and
replacing the dummy gate with a replacement gate, wherein portions of the nanowires surrounded by the replacement gate serve as channels of the FET.
10. The method of claim 9 , further comprising the step of:
forming spacers on opposite sides of the dummy gate.
11. The method of claim 9 , wherein the dummy gate comprises poly-silicon.
12. The method of claim 9 , wherein the epitaxial germanium is interdiffused with the silicon in the nanowires and pads using thermal mixing.
13. The method of claim 9 , further comprising the step of:
further increasing a concentration of germanium in the silicon germanium regions using germanium condensation.
14. The method of claim 9 , wherein the epitaxial germanium is grown on the portions of the nanowires extending out from under the gate and the portion of the pads at a temperature of about 300° C. in the presence of a germanium precursor.
15. The method of claim 14 , wherein the germanium precursor comprises germane.
16. The method of claim 9 , wherein the replacement gate comprises a metal gate material.
17. The method of claim 9 , wherein removal of the dummy gate forms a trench in the dielectric film and exposes the thermal oxide over the nanowires, the method further comprising the step of:
replacing the thermal oxide over the nanowires with a gate dielectric.
18. The method of claim 9 , wherein the replacement gate is a surrounding gate.
19. The method of claim 9 , wherein the replacement gate is an omega gate.
20. The method of claim 9 , further comprising the step of:
doping the embedded silicon germanium source and drain regions using one of in-situ doping and ion-implantation.