IP Library Granted Patent US 8,252,662
Granted Patent B1
US 8,252,662 · App. 12/749,476 · Granted Aug 28, 2012

Method and structure for manufacture of light emitting diode devices using bulk GaN

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Quick Facts
Patent No.
US 8,252,662
App. No.
12/749,476
Granted
Aug 28, 2012
Kind
B1
Abstract

A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure. The method also includes subjecting the gallium nitride containing bulk crystalline substrate material to at least one etching process to selectively remove crystalline material underlying the etch stop layer, wherein the etch stop layer is exposed, and the etch stop layer remains substantially intact.

Claims (34)

1. A method for fabricating a plurality of light emitting diodes (LEDs) comprising:

providing a non-polar or semi-polar bulk crystalline substrate which includes gallium nitride, and which has a front surface and a back surface separated by a first thickness;

forming a precursor structure for the LEDs on the substrate by forming an AlGaN filter layer with a lower Al % percentage than that in the overlying layers over the front surface, an n-type layer over the filter layer, an active region layer over the n-type layer, a p-type layer over the active region layer, and a metallization layer over the p-type layer;

removing material from the back surface of the substrate to reduce the substrate to a second thickness;

dividing the substrate and overlying layers into separate LED devices;

mounting the LED devices to a carrier structure having an upper surface with the metallization layer on each LED device in contact with the carrier structure; and

etching, using bandgap-selective photoelectrochemical etching, the substrate to a thickness of 3-4 μm.

2. The method of claim 1 wherein the step of dividing the substrate comprises at least one of scribing, dicing, cleaving, and breaking.

3. The method of claim 1 wherein the step of mounting the LED devices to a carrier structure comprises eutectic bonding.

4. The method of claim 1 wherein the n-type layer and the p-type layer each comprise GaN.

5. The method of claim 4 wherein the active region layer comprises InGaN.

6. The method of claim 5 wherein after the step of mounting the LED devices to a carrier a step is performed of depositing filler material at least between the LEDs.

7. The method of claim 6 further comprising removing the filler material after the step removing the substrate down to a thickness of 3-4 μm.

8. A method for fabricating a plurality light emitting diodes (LEDs) comprising:

providing a gallium nitride substrate with a non-polar or semi-polar crystallographic orientation, the substrate having a front surface and a back surface separated by a first thickness;

forming a precursor structure for the LEDs on the substrate by forming an sacrificial layer over the surface region, an n-type layer over the sacrificial layer, an active region over the n-type layer, a p-type layer over the active region, and a metallization layer over the p-type layer;

dividing the precursor structure into separate LEDs by etching channels in the structure which extend through the metallization layer, the p-type layer, the active region, and the n-type layer, to the sacrificial layer;

attaching a submount to the metallization layer on the precursor structure;

laterally etching the sacrificial layer to enable removal of the substrate;

removing the substrate, and

dividing the submount and overlying layers into separate LED devices

wherein the step of dividing the precursor structure into separate LEDs by etching channels in the structure further comprises:

in a first etching step etching the metallization layer, the p-type layer, and the active region to thereby form mesa structures having sidewalls; and

in a second etching step etching the n-type layer.

9. The method of claim 8 further comprising a step of passivating the sidewalls of the mesa structures before performing the second etching step.

10. The method of claim 9 wherein the step of passivating the sidewalls comprises oxidizing the sidewalls.

11. The method of claim 8 wherein the step of laterally etching the sacrificial layer comprises performing a photoelectrochemical etching process.

12. The method of claim 8 further comprising after the step of removing the substrate, the substrate which has been removed is reused in the step of providing a gallium nitride substrate with a non-polar or semi-polar crystallographic orientation.

13. The method of claim 8 wherein the sacrificial layer comprises indium gallium.

14. The method of claim 13 wherein the sacrificial layer comprises InGaN.

15. The method of claim 8 wherein the substrate has a first band gap energy and the sacrificial layer has a second band gap energy less than the first band gap energy.

16. The method of claim 8 wherein the step of laterally etching the sacrificial layer to enable removal of the substrate comprises performing a photoelectrochemical etching process.

17. The method of claim 8 wherein the n-type layer and the p-type layer each comprise GaN.

18. The method of claim 17 wherein the active layer comprises InGaN.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Feb 20, 2020
From: SPECIAL VALUE CONTINUATION PARTNERS, LP; TENNENBAUM OPPORTUNITIES PARTNERS V, LP; TCPC SBIC, LP; EL DORADO INVESTMENT COMPANY; TENNEBAUM CAPITAL PARTNERS, LLC
To: SORAA, INC.
Reel/Frame 051974/0413 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2019
From: SORAA, INC.
To: SLT TECHNOLOGIES, INC.
Reel/Frame 051210/0211 →
SECURITY INTEREST Recorded Sep 5, 2014
From: SORAA, INC.
To: SPECIAL VALUE CONTINUATION PARTNERS, LP; TENNENBAUM OPPORTUNITIES PARTNERS V, LP; TCPC SBIC, LP
Reel/Frame 033691/0582 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY COLLATERAL AT REEL/FRAME NO. 32148/0851 Recorded Aug 29, 2014
From: BRIDGE BANK, NATIONAL ASSOCIATION
To: SORAA, INC.
Reel/Frame 033664/0560 →
SECURITY AGREEMENT Recorded Jan 31, 2014
From: SORAA, INC.
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 032148/0851 →
CORRECTIVE ASSIGNMENT TO CORRECT THE THE "ASSIGNORS" SECTION NEEDS TO BE CORRECTED TO ADD THE OTHER FOUR INVENTORS. THERE ARE A TOTAL OF FIVE INVENTORS. PREVIOUSLY RECORDED ON REEL 024249 FRAME 0203. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT TO SORAA, INC.. Recorded Apr 28, 2010
From: POBLENZ, CHRISTIANE; SCHMIDT, MATHEW C.; FEEZELE, DANIEL F.; RARING, JAMES W.; SHARMA, RAJAT
To: SORAA, INC.
Reel/Frame 024306/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2010
From: POBLENZ, CHRISTIANE
To: SORAA, INC.
Reel/Frame 024249/0203 →