DSP engine with implicit mixed sign operands
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
1. A processor, comprising:
at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode;
a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
2. The processor according to claim 1 , wherein the multiplier unit comprises an n-bit multiplier controllable to perform a signed, an unsigned, or a mixed sign multiplication of two input operands.
3. The processor according to claim 2 , wherein the first operand is selected from a first set of two consecutive registers and the second operand is selected from a second set of two consecutive registers.
4. The processor according to claim 1 , wherein the multiplier unit comprises:
a multiplier data pre-processor coupled to the multiplier unit to independently sign or zero extend the two input operands, and
a signed multiplier.
5. The processor according to claim 4 , wherein
in signed mode, the multiplier data pre-processor signed extends all input data,
in unsigned mode, multiplier data pre-processor zero extends all input data, and
in mixed sign mode, the multiplier mode decoder directs the multiplier data pre-processor to sign extend an input if its source is an odd register number or odd memory address, or zero extend an input if its source is an even register number or even memory address.
6. The processor according to claim 4 , wherein the signed multiplier is an n+1 bit multiplier.
7. The processor according to claim 1 , further comprising a control register to select the signed mode, the unsigned mode, or the mixed sign mode in which an automatic selection of signed, unsigned, or combined sign/unsigned multiplication is performed.
8. The processor according to claim 1 , wherein the location information comprises whether a register is an odd or an even register from a plurality of working registers.
9. The processor according to claim 1 , wherein first and second operands are supplied by a data memory and the location information comprises whether an address is an odd or an even address in memory.
10. The processor according to claim 1 , further comprising a barrel shifter having a size to accommodate at least the size of a result generated by the multiplier.
11. The processor according to claim 10 , further comprising an adder coupled with at least one accumulator and the barrel shifter, wherein the multiplier, accumulator, barrel shifter are part of a digital signal processing (DSP) engine.
12. The processor according to claim 11 , further comprising a result extension unit coupled between the multiplier and the barrel shifter and a zero-backfill unit coupled with the result extension unit.
13. The processor according to claim 11 , further comprising round logic coupled with the accumulator.
14. The processor according to claim 11 , wherein the DSP engine is a 16-bit DSP engine having a plurality of 16-bit registers and wherein the barrel shifter and the accumulator each comprise 40-bit.
15. The processor according to claim 11 , further comprising a microcontroller unit wherein at least the multiplier is shared by the microcontroller unit and the DSP to execute arithmetic microcontroller instructions.
16. A method for performing a multiplication in a processor comprising the steps of
providing a first n-bit operand from a first location to a multiplier unit, wherein the multiplier unit can be controlled to operate in signed, unsigned, or a combined sign/unsigned mode;
providing a second operand from a second location to the multiplier unit;
decoding the location for the first and second operand and controlling the multiplier unit to operate in a mixed mode in which a signed, an unsigned, or a combined sign/unsigned multiplication is performed depending on the locations.
17. The method according to claim 16 , wherein the first and second operands are stored in registers and the location comprises whether a register is an odd or an even register from a plurality of working registers.
18. The method according to claim 16 , wherein first and second operands are supplied by a data memory and the location comprises whether an address is an odd or an even address in memory.
19. The method according to claim 17 , wherein the first operand is selected from a first set of two consecutive registers and the second operand is selected from a second set of two consecutive registers.
20. The method according to claim 16 , wherein a control register determines whether the multiplier unit operates in the a signed, an unsigned, or the mixed mode.
21. The method according to claim 20 , wherein the multiplier unit comprises a signed multiplier and:
in signed mode, the first and second operands are signed extended,
in unsigned mode, the first and second operands are zero extended, and
in mixed sign mode, the first or second operand is sign extended if it is supplied by an odd register number or odd memory address, or zero extended if it is supplied by an even register number or even memory address.
22. A method for performing a 2n-bit multiplication using 4 n-bit data words, comprising the steps of:
storing a first operand of the 2n-bit multiplication in a first set of two consecutive registers or two consecutive memory locations;
storing a second operand of the 2n-bit multiplication in a second set of two consecutive registers or two consecutive memory addresses;
performing a first multiplication by a controllable multiplier unit using a first register or memory address of the first set and a first register or memory address of the second set and shifting an associated first result,
performing a second multiplication by the controllable multiplier unit using the first register or memory address of the first set and a second register or memory address of the second set to generate an associated second result,
performing a third multiplication by the controllable multiplier unit using the first register or memory address of the second set and a second register or memory address of the first set to generate an associated third result,
wherein for each multiplication, the multiplier unit is automatically controlled to operate in signed, unsigned, or a combined sign/unsigned mode by decoding the location of the register or address;
adding the first, second and third result to generate an end result and storing the end result in registers or memory.
23. The method according to claim 22 , wherein the location comprises whether a register is an odd or an even register from a plurality of working registers.
24. The method according to claim 22 , wherein the location comprises whether an address is an odd or an even address in memory.
25. The method according to claim 22 , wherein a control register determines whether the multiplier operates in signed, unsigned, or a mixed sign mode.
26. The method according to claim 25 , wherein
in signed mode, all inputs to a multiplier are signed extended, and
in mixed sign mode, an input to the multiplier is sign extended if it is supplied by an odd register number or odd memory address, or zero extended if it is supplied by an even register number or even memory address.
27. The method according to claim 22 , wherein the second and third results are shifted and further comprising the step of performing a fourth multiplication by the controllable multiplier using the second register or memory address of the first set and the second register or memory address of the second set to generate an associated fourth result, and wherein the fourth result is added to the first, second, and third result to generate the end result.
28. The method according to claim 27 , wherein a control register determines whether the multiplier unit operates in signed, unsigned, or a mixed sign mode.
29. The method according to claim 28 , wherein the multiplier unit comprises a signed multiplier and:
in signed mode, all inputs to the multiplier are signed extended,
in unsigned mode, all input to the multiplier are zero extended, and
in mixed sign mode, an input to the multiplier is sign extended if it is supplied by an odd register number or odd memory address, or zero extended if it is supplied by an even register number or even memory address.