IP Library Granted Patent US 8,105,872
Granted Patent B2
US 8,105,872 · App. 12/792,066 · Granted Jan 31, 2012

Semiconductor device and method of forming prefabricated EMI shielding frame with cavities containing penetrable material over semiconductor die

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Quick Facts
Patent No.
US 8,105,872
App. No.
12/792,066
Granted
Jan 31, 2012
Kind
B2
Abstract

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Claims (54)

1. A method of making a semiconductor device, comprising:

providing a temporary carrier;

mounting a plurality of first semiconductor die to the temporary carrier;

providing a prefabricated electromagnetic interference (EMI) shielding frame having a plate and integrated bodies extending from the plate, the bodies defining a plurality of cavities in the shielding frame;

depositing penetrable material in the cavities of the shielding frame;

mounting the shielding frame over the first semiconductor die such that the penetrable material encapsulates the first semiconductor die;

removing the temporary carrier;

forming a first interconnect structure over the first semiconductor die, shielding frame, and penetrable material, the bodies of the shielding frame being electrically connected through the first interconnect structure to a ground point; and

singulating the shielding frame through the bodies to separate the first semiconductor die.

2. The method of claim 1 , wherein the first semiconductor die is a flipchip type semiconductor die.

3. The method of claim 1 , further including forming a thermal interface material over a surface of the first semiconductor die adjacent to the plate of the shielding frame.

4. The method of claim 1 , further including mounting a heat sink over the plate of the shielding frame.

5. The method of claim 1 , further including:

forming a second interconnect structure over the shielding frame; and

mounting a second semiconductor die to the second interconnect structure.

6. The method of claim 1 , further including planarizing the plate of the shielding frame.

7. A method of making a semiconductor device, comprising:

providing a carrier;

mounting a first semiconductor die to the carrier;

providing a shielding frame having a plate and a plurality of integrated bodies extending from the plate, wherein a first body defines a cavity in the shielding frame;

depositing penetrable material in the cavity of the shielding frame;

mounting the shielding frame over the first semiconductor die such that the penetrable material encapsulates the first semiconductor die;

removing the carrier; and

forming a first interconnect structure over the first semiconductor die, shielding frame, and penetrable material.

8. The method of claim 7 , further including:

depositing the penetrable material around a second body of the shielding frame; and

removing a portion of the plate to separate the second body from the first body, the second body providing a z-direction conductive pillar through the penetrable material.

9. The method of claim 8 , further including:

forming a second interconnect structure over the shielding frame; and

mounting a second semiconductor die to the second interconnect structure, the second semiconductor die being electrically connected through the second interconnect structure to the z-direction conductive pillar.

10. The method of claim 8 , wherein the z-direction conductive pillar is electrically connected to the first interconnect structure.

11. The method of claim 7 , wherein the first body is electrically connected through the first interconnect structure to a ground point.

12. The method of claim 7 , further including:

forming a thermal interface material over a surface of the first semiconductor die adjacent to the plate of the shielding frame; and

mounting a heat sink over the plate of the shielding frame.

13. The method of claim 7 , wherein the shielding frame covers a plurality of first semiconductor die.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

providing a shielding frame having a plate and a plurality of integrated bodies extending from the plate, wherein a first body defines a cavity in the shielding frame;

depositing penetrable material in the cavity of the shielding frame;

mounting the shielding frame over the first semiconductor die such that the penetrable material encapsulates the first semiconductor die; and

forming a first interconnect structure over the first semiconductor die, shielding frame, and penetrable material.

15. The method of claim 14 , further including:

depositing the penetrable material around a second body of the shielding frame; and

removing a portion of the plate to separate the second body from the first body, the second body providing a z-direction conductive pillar through the penetrable material.

16. The method of claim 15 , further including:

forming a second interconnect structure over the shielding frame; and

mounting a second semiconductor die to the second interconnect structure, the second semiconductor die being electrically connected through the second interconnect structure to the z-direction conductive pillar.

17. The method of claim 15 , wherein the z-direction conductive pillar is electrically connected to the first interconnect structure.

18. The method of claim 14 , wherein the first body is electrically connected through the first interconnect structure to a ground point.

19. The method of claim 14 , further including:

forming a thermal interface material over a surface of the first semiconductor die adjacent to the plate of the shielding frame; and

mounting a heat sink over the plate of the shielding frame.

20. The method of claim 14 , further including forming a plurality of openings in the plate of the shielding frame as an escape for excess penetrable material.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0272. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0272 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2010
From: PAGAILA, REZA A.; LIN, YAOJIAN
To: STATS CHIPPAC, LTD.
Reel/Frame 024470/0980 →