Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
View Patent ↗A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.
1. A method of making a semiconductor device, comprising:
providing a substrate including a plurality of lead fingers with a surface disposed at a same level around a die area;
forming a first conductive layer over the surface of a first set of the lead fingers;
forming a second conductive layer over the surface of a second set of the lead fingers, each second conductive layer being positioned adjacent to the first conductive layer and each first conductive layer being positioned adjacent to the second conductive layer, the second conductive layer including a thickness greater than a thickness of the first conductive layer;
forming a plurality of bumps over the first and second conductive layers with a width of the bumps greater than a width of the first and second conductive layers and the bumps formed over the first conductive layer overlapping the bumps formed over the second conductive layer while the bumps remain physically separated by the thickness of the second conductive layer being greater than the thickness of the first conductive layer; and
forming a plurality of bond wires electrically connected to the bumps.
2. The method of claim 1 , further including:
forming the first conductive layer to a thickness of 5 micrometers; and
forming the second conductive layer to a thickness of 25 micrometers.
3. The method of claim 1 , wherein a pitch between the first and second conductive layers is less than 60 micrometers.
4. The method of claim 1 , further including forming a masking layer over the substrate with openings over the first and second conductive layers prior to forming the bumps.
5. The method of claim 1 , further including forming the first and second conductive layers in a side-by-side arrangement or staggered arrangement.
6. The method of claim 1 , further including:
disposing a semiconductor die over the die area of the substrate; and
electrically connecting contact pads formed on the semiconductor die to the bond wires.
7. The method of claim 6 , wherein the lead fingers extend under a footprint of the semiconductor die.
8. A method of making a semiconductor device, comprising:
providing a substrate having a plurality of lead fingers;
forming a first conductive layer over the lead fingers;
forming a second conductive layer over the lead fingers, the first and second conductive layers being interposed in an alternating arrangement with respect to each other, the second conductive layer including a thickness different than a thickness of the first conductive layer; and
forming an interconnect structure over the first conductive layer and second conductive layer with a width of the interconnect structure greater than a width of the first and second conductive layers and the interconnect structure formed over the first conductive layer overlapping the interconnect structure formed over the second conductive layer.
9. The method of claim 8 , further including:
forming the first conductive layer to a thickness of 5 micrometers; and
forming the second conductive layer to a thickness of 25 micrometers.
10. The method of claim 8 , wherein a pitch between the first and second conductive layers is less than 60 micrometers.
11. The method of claim 8 , further including forming the first and second conductive layers in a side-by-side arrangement or staggered arrangement.
12. The method of claim 8 , wherein forming the interconnect structure includes forming a bump, stud bump, conductive post, or conductive pillar over the first conductive layer and second conductive layer.
13. The method of claim 12 , further including forming a bond wire electrically connected to the bumps.
14. A method of making a semiconductor device, comprising:
providing a substrate having a plurality of lead fingers; and
forming a bump on trace (BOT) interconnect structure over the lead fingers by,
(a) forming a first conductive layer over the lead fingers,
(b) forming a second conductive layer over the lead fingers, the first and second conductive layers being interposed in an alternating arrangement with respect to each other, the second conductive layer comprising a height different than a height of the first conductive layer, and
(c) forming a plurality of bumps over the first and second conductive layers with a width of the bumps greater than a width of the first and second conductive layers and the bumps formed over the first conductive layer overlapping the bumps formed over the second conductive layer.
15. The method of claim 14 , wherein forming the interconnect structure includes:
forming a first bump over the first conductive layer;
forming a second bump over the second conductive layer;
forming a first bond wire electrically connected to the first bump; and
forming a second bond wire electrically connected to the second bump.
16. The method of claim 15 , further including:
disposing a semiconductor die over a die area of the substrate;
electrically connecting a first contact pad formed on the semiconductor die to the first bond wire; and
electrically connecting a second contact pad formed on the semiconductor die to the second bond wire.
17. The method of claim 16 , wherein the lead fingers extend under a footprint of the semiconductor die.
18. The method of claim 14 , further including forming the first and second conductive layers in a side-by-side arrangement or staggered arrangement.
19. The method of claim 14 , further including:
forming the first conductive layer to a height of 5 micrometers; and
forming the second conductive layer to a height of 25 micrometers.
20. The method of claim 14 , further including forming a masking layer over the substrate with an opening over the first conductive layer prior to forming the interconnect structure.
21. A method of making a semiconductor device, comprising:
providing a substrate adapted for mounting a semiconductor die for structural support and interconnection, the substrate including,
a first lead finger comprising a first height, and
a second lead finger adjacent to the first lead finger and comprising a second height different from the first height of the first lead finger;
forming a first interconnect structure over the first lead finger; and
forming a second interconnect structure over the second lead finger with a width of the first and second interconnect structures greater than a width of the first and second lead fingers and the first interconnect structure overlapping the second interconnect structure.
22. The method of claim 21 , wherein the first interconnect structure further includes a bump, stud bump, conductive pillar, or conductive post formed on the first lead finger of the structure.
23. The method of claim 21 , wherein the first interconnect structure further includes a wire bond bump and a bond wire.
24. The method of claim 21 , further including a second interconnect structure formed over the second lead finger and electrically isolated from the first interconnect structure, wherein an outer dimension of the first interconnect structure overlaps in a plan view an outer dimension of the second interconnect structure.
25. The method of claim 21 , wherein the width of the first interconnect structure is greater than a pitch between the first lead finger of the structure and the second lead finger of the structure.