IP Library Granted Patent US 7,893,684
Granted Patent B2
US 7,893,684 · App. 12/848,937 · Granted Feb 22, 2011

Integrated power detector with temperature compensation for fully-closed loop control

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Quick Facts
Patent No.
US 7,893,684
App. No.
12/848,937
Granted
Feb 22, 2011
Kind
B2
Abstract

An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.

Claims (23)

1. A power detector comprising:

a detection power input circuit for receiving an RF signal, said detection power input circuit comprises;

a first resistor including a first terminal for receiving the RF signal and including a second terminal,

a first capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal, and

a second resistor including a first terminal coupled to the second terminal of the first capacitor and including a second terminal;

a bias circuit including an output for generating a bias signal in response to a reference control voltage, said bias circuit comprising;

a third resistor including a first terminal coupled to a reference voltage terminal and including a second terminal coupled to the second terminal of the second resistor,

a first bipolar transistor including a collector coupled to the second terminal of the third resistor, a base coupled to said collector, and an emitter, and

a fourth resistor including a first terminal coupled to the emitter of the first bipolar transistor and including a second terminal coupled to a ground terminal;

a detection circuit, having a second bipolar transistor having a collector, emitter and base, for generating a power control voltage at the emitter, having a voltage characteristic that offsets temperature characteristics of the received RF signal, which can be adjusted independently by the size of the first and second bipolar transistors, with the detection circuit forming a current mirror with the bias circuit, wherein said detection circuit comprises;

said second bipolar transistor including a collector coupled to a voltage supply terminal, including a base coupled to the first terminal of the second resistor, and including an emitter,

a fifth resistor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal coupled to the ground terminal,

a second capacitor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal coupled to the ground terminal, and

a sixth resistor including a first terminal coupled to the emitter of the second bipolar transistor and including a second terminal for providing the detector voltage output;

wherein the detection circuit operates as a current mirror circuit to the bias circuit with temperature compensation which is independently adjustable by the fourth resistor and the fifth resistor.

2. The power detector of claim 1 wherein the detection circuit is further arranged as an emitter follower for enveloping the RF signal.

3. The power detector of claim 1 wherein the bias circuit provides DC compensation to a power amplifier coupled thereto.

4. The power detector of claim 1 wherein a power amplifier is coupled to the bias circuit, the power amplifier including a driver stage providing said RF signal.

5. The power detector of claim 1 wherein the detection power input circuit, the bias circuit, the detection circuit, and a power amplifier are formed on a single integrated circuit.

6. The power detector of claim 4 wherein the detection circuit compensates temperature variation of an inputted detection voltage.

7. The power detector of claim 6 wherein the inputted detection voltage is received from an interstage of a power amplifier.

8. The power detector of claim 4 wherein the power amplifier comprises a driver stage and a power stage.

9. The power detector of claim 1 , wherein the emitter of the first bipolar transistor is not directly electrically connected to the emitter of the second bipolar transistor.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2011
From: SILICON STORAGE TECHNOLOGY, INC.
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 026213/0515 →