Three-dimensional integrated circuit structure
View Patent ↗A method of forming a semiconductor structure includes coupling a semiconductor structure to an interconnect region through a bonding region. The interconnect region includes a conductive line in communication with the bonding region. The bonding region includes a metal layer which covers the interconnect region. The semiconductor structure is processed to form a vertically oriented semiconductor device.
1. A method, comprising:
forming a conductive bonding region which is carried by an interconnect region; and
coupling a multiple layer semiconductor structure to the interconnect region through the conductive bonding region, wherein the multiple layer semiconductor structure is carried by a support structure, and a porous silicon detach region extends between the support structure and multiple layer structure.
2. The method of claim 1 , further including processing the multiple layer semiconductor structure to form a mesa structure bonded to the interconnect region through a contact region.
3. The method of claim 1 , wherein the multiple layer semiconductor structure includes single crystalline semiconductor material.
4. The method of claim 1 , further including forming the multiple layer semiconductor structure by depositing a blanket layer of semiconductor material on the detach region.
5. The method of claim 1 , wherein the interconnect region includes a conductive line in communication with the conductive bonding region.
6. The method of claim 1 , further including forming the bonding region by forming a metal layer on the interconnect region.
7. The method of claim 1 , wherein the bonding region covers a major surface of the interconnect region.
8. The method of claim 2 , further including processing the mesa structure to form a vertically oriented semiconductor device.
9. The method of claim 2 , wherein the interconnect region includes a conductive line in communication with the contact region.
10. The method of claim 2 , wherein the contact region is formed in response to removing a portion of the conductive bonding region.
11. A method, comprising:
providing an interconnect region carried by an electronic circuit;
forming a metal bonding region on the interconnect region;
providing a substrate which includes a support structure which carries a multiple layer semiconductor structure. wherein the substrate includes a detach region between the support structure and multiple layer structure and the detach region includes porous silicon; and
coupling the multiple layer structure to the interconnect region through the metal bonding region.
12. The method of claim 11 , wherein the multiple layer structure is coupled to the interconnect region by establishing a bonding interface between the metal bonding region and semiconductor material of the multiple layer semiconductor structure.
13. The method of claim 11 , wherein the multiple layer structure includes single crystal semiconductor material.
14. The method of claim 11 , further including removing the support structure from the multiple layer structure so the multiple layer structure is carried by the interconnect region.
15. The method of claim 11 , further including processing the multiple layer structure to form a mesa structure.
16. The method of claim 12 , wherein the interconnect region includes a conductive line in communication with the metal bonding region.
17. A method, comprising:
coupling a multi layer semiconductor structure to an interconnect region through a bonding region which includes a metal, wherein the multiple layer semiconductor structure is coupled to a support structure by a porous silicon detach region;
wherein the interconnect region includes a conductive line in communication with the bonding region.
18. The method of claim 17 , wherein the interconnect region includes a plurality of conductive lines in communication with the bonding region.
19. The method of claim 17 , further including separating the multilayer semiconductor structure from the support substrate so the semiconductor structure is carried by the interconnect region.
20. The method of claim 17 , wherein the multilayer semiconductor structure includes a planarized surface facing the bonding region.
21. The method of claim 17 , further including forming the bonding region by forming a blanket metal layer on the interconnect region.
22. The method of claim 17 , wherein the multilayer semiconductor structure includes single crystal semiconductor material.
23. The method of claim 17 , wherein the multilayer semiconductor structure includes a pn junction.
24. The method of claim 17 , wherein the bonding region covers a major surface of the interconnect region.
25. The method of claim 19 , wherein the multilayer semiconductor structure includes a cleaved surface facing away from the bonding region.