IP Library Granted Patent US 8,409,922
Granted Patent B2
US 8,409,922 · App. 12/882,110 · Granted Apr 2, 2013

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Inventors: Zigmund R. Camacho (Singapore, SG); Dioscoro A. Merilo (Singapore, SG); Henry D. Bathan (Singapore, SG); Emmanuel A. Espiritu (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
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Quick Facts
Patent No.
US 8,409,922
App. No.
12/882,110
Granted
Apr 2, 2013
Kind
B2
Abstract

A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Claims (70)

1. A method of making a semiconductor device, comprising:

providing a substrate having a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate;

mounting a first semiconductor die over the substrate;

providing a leadframe having a base plate and a plurality of base leads extending from the base plate;

forming an etch-resistant conductive layer over a surface of the base plate opposite the base leads;

mounting the leadframe to the substrate over the first semiconductor die;

depositing an encapsulant over the substrate and first semiconductor die;

removing the base plate while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads; and

forming an interconnect structure over a surface of the substrate opposite the base leads.

2. The method of claim 1 , further including mounting a second semiconductor die over the first semiconductor die prior to mounting the leadframe.

3. The method of claim 1 , further including depositing an underfill material under the first semiconductor die.

4. The method of claim 1 , further including:

forming a window in the base plate; and

depositing the encapsulant through the window.

5. The method of claim 1 , further including:

forming an opening in the base plate; and

depositing the encapsulant through the opening.

6. The method of claim 1 , wherein the substrate includes a bismaleimide/triazine laminate and epoxy resin.

7. A method of making a semiconductor device, comprising:

providing a substrate;

mounting a first semiconductor die over the substrate;

providing an interposer having a base plate and a plurality of base leads extending from the base plate;

forming a conductive layer over a surface of the base plate opposite the base leads;

mounting the interposer to the substrate over the first semiconductor die;

depositing an encapsulant over the substrate and first semiconductor die; and

removing the base plate while retaining the conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads.

8. The method of claim 7 , further including forming an interconnect structure over a surface of the substrate opposite the base leads.

9. The method of claim 7 , further including mounting a second semiconductor die over the first semiconductor die prior to mounting the interposer.

10. The method of claim 7 , further including mounting a second semiconductor die or component over the encapsulant electrically connected to the conductive layer and base leads.

11. The method of claim 10 , wherein the second semiconductor die or component includes a wire-bond semiconductor die.

12. The method of claim 7 , further including:

forming a window in the base plate; and

depositing the encapsulant through the window.

13. The method of claim 7 , wherein the conductive layer includes an etch-resistant material.

14. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a first semiconductor die over the first substrate;

providing a second substrate including a base plate and a plurality of base leads extending from the base plate;

forming a conductive layer over a surface of the base plate opposite the base leads;

disposing the second substrate over the first substrate and first semiconductor die;

depositing an encapsulant over the first substrate and first semiconductor die; and

removing a first portion of the base plate while retaining a second portion of the base plate opposite the base leads to electrically isolate the base leads.

15. The method of claim 14 , wherein the conductive layer includes an etch-resistant material.

16. The method of claim 14 , further including forming an interconnect structure over a surface of the first substrate opposite the base leads.

17. The method of claim 14 , further including disposing a second semiconductor die over the first semiconductor die.

18. The method of claim 14 , further including disposing a second semiconductor die or component over the encapsulant electrically connected to the base leads.

19. The method of claim 18 , wherein the second semiconductor die or component includes a wire-bond semiconductor die.

20. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a first semiconductor die over the first substrate;

providing a second substrate including a base plate and a plurality of base leads extending from the base plate;

forming an etch-resistant material over a surface of the base plate opposite the base leads;

disposing the second substrate over the first substrate and first semiconductor die; and removing a portion of the base plate outside the etch-resistant material to electrically isolate the base leads.

21. The method of claim 20 , further including removing a portion of the base plate outside the etch-resistant material to electrically isolate the base leads.

22. The method of claim 20 , further including depositing an encapsulant over the first substrate and first semiconductor die.

23. The method of claim 22 , further including disposing a second semiconductor die or component over the encapsulant.

24. The method of claim 23 , wherein the second semiconductor die or component includes a wire-bond semiconductor die.

25. The method of claim 22 , further including:

forming an opening in the base plate; and

depositing the encapsulant through the opening.

26. The method of claim 22 , further including:

forming a window in the base plate; and

depositing the encapsulant through the window.

27. The method of claim 20 , further including forming an interconnect structure over a surface of the first substrate opposite the base leads.

28. The method of claim 20 , further including disposing a second semiconductor die over the first semiconductor die.

29. The method of claim 20 , further including disposing a second semiconductor die over the base leads.

30. The method of claim 20 , further including depositing an underfill material under the first semiconductor die.

31. The method of claim 20 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the base leads and first substrate.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2010
From: CAMACHO, ZIGMUND R.; MERILO, DIOSCORO A.; BATHAN, HENRY D.; ESPIRITU, EMMANUEL A.
To: STATS CHIPPAC, LTD.
Reel/Frame 024986/0773 →
Continuity (1)
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