IP Library Granted Patent US 8,421,212
Granted Patent B2
US 8,421,212 · App. 12/887,681 · Granted Apr 16, 2013

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Inventors: Kang Chen (Singapore, SG); Xusheng Bao (Singapore, SG); Rui Huang (Singapore, SG); Yung Kuan Hsiao (Singapore, SG); Hin Hwa Goh (Singapore, SG)
Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,421,212
App. No.
12/887,681
Granted
Apr 16, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Claims (61)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side;

mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side;

forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side;

forming a top re-passivation layer over the structure top side and the encapsulation, the top re-passivation layer having a hole; and

mounting a heat sink over the top re-passivation layer for removing heat from the active side, the heat sink having a protrusion on the active side and within the hole.

2. The method as claimed in claim 1 wherein mounting the heat sink includes mounting the heat sink, the heat sink larger than the integrated circuit.

3. The method as claimed in claim 1 wherein:

mounting the heat sink includes mounting the heat sink connected to the structure top side; and

further comprising:

connecting an external connector to the structure bottom side, the heat sink grounded through the external connector.

4. The method as claimed in claim 1 wherein mounting the heat sink includes mounting the heat sink having a protrusion on the active side.

5. A method of manufacture of an integrated circuit packaging system comprising:

providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side;

mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side;

forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side;

forming a top redistribution line electrically connected to the structure top side and the active side;

forming a top re-passivation layer over the structure top side and the encapsulation, the top re-passivation layer directly on the top redistribution line; and

mounting a heat sink over the top re-passivation layer for removing heat from the active side.

6. The method as claimed in claim 5 further comprising:

forming a thermal interface directly on the active side; and

wherein:

mounting the heat sink includes mounting the heat sink directly on the thermal interface.

7. The method as claimed in claim 5 further comprising:

forming a thermal interface directly on the top re-passivation layer; and

wherein:

mounting the heat sink includes mounting the heat sink directly on the thermal interface.

8. The method as claimed in claim 5 further comprising:

attaching a conductive connector to the active side; and

wherein:

mounting the heat sink includes mounting the heat sink directly on the conductive connector.

9. The method as claimed in claim 5 wherein providing the interconnect structure includes providing the interconnect structure having a vertical interconnect between the structure bottom side and the structure top side.

10. An integrated circuit packaging system comprising:

an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side;

an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side;

an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side;

a top re-passivation layer over the structure top side and the encapsulation, the top re-passivation layer having a hole; and

a heat sink over the top re-passivation layer for removing heat from the active side, the heat sink having a protrusion on the active side and within the hole.

11. The system as claimed in claim 10 wherein the heat sink is larger than the integrated circuit.

12. The system as claimed in claim 10 wherein:

the heat sink is connected to the structure top side; and

further comprising:

an external connector connected to the structure bottom side, the heat sink grounded through the external connector.

13. The system as claimed in claim 10 wherein the heat sink has a protrusion on the active side.

14. The system as claimed in claim 10 further comprising:

a top redistribution line electrically connected to the structure top side and the active side; and

wherein:

the top re-passivation layer is directly on the top redistribution line.

15. The system as claimed in claim 14 further comprising:

a thermal interface directly on the active side; and

wherein:

the heat sink is directly on the thermal interface.

16. The system as claimed in claim 14 further comprising:

a thermal interface directly on the top re-passivation layer; and

wherein:

the heat sink is directly on the thermal interface.

17. The system as claimed in claim 14 further comprising:

a conductive connector attached to the active side; and

wherein:

the heat sink is directly on the conductive connector.

18. The system as claimed in claim 14 wherein the interconnect structure has a vertical interconnect between the structure bottom side and the structure top side.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2010
From: CHEN, KANG; BAO, XUSHENG; HUANG, RUI; HSIAO, YUNG KUAN; GOH, HIN HWA
To: STATS CHIPPAC LTD.
Reel/Frame 025070/0987 →
Continuity (1)
Related Publication 20120068328A1 · Mar 22, 2012