Circuit with ESD protection for a switching regulator
View Patent ↗The present invention discloses a circuit with ESD protection and high voltage conversion for a switching regulator. It mainly comprises a non-overlap circuit, a power P-type MOS device, a parasitic diode, a digital logic AND gate, a pair of resistance and capacitance, a power N-type MOS device, an ESD N-type MOS device, a Lx pin and an ESD protection cell. The present invention can effectively decrease the on-resistance of MOS device and then improve the circuit efficiency.
1. A circuit with ESD protection for a switching regulator, comprising:
a non-overlap circuit, having a first output terminal and a second output terminal, the first output terminal outputting a signal of default A and the second output terminal outputting a signal of default B;
a power P-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the first output terminal of the non-overlap circuit and receiving the signal of default A outputted from the first output terminal of the non-overlap circuit;
a diode, electrically connected to the source terminal and the drain terminal of the power P-type MOS device, used for providing a pathway for an electrostatic discharge;
a digital logic AND gate, having two input terminals and a output terminal, one of the input terminals electrically connected to the second output terminal of the non-overlap circuit and receiving the signal of default B from the second output terminal of the non-overlap circuit, the other one of the input terminals receiving a EN signal, the output terminal providing a output signal of the digital logic AND gate;
a power N-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the output terminal of the digital logic gate of AND gate and receiving the output signal of the digital logic AND gate, the drain terminal electrically connected to the drain terminal of the power P-type MOS device, the source terminal electrically connected to a ground;
a Lx pin, electrically connected to the drain terminal of the power P-type MOS device and the drain terminal of the power N-type MOS device, used for outputting a converted voltage; and
an ESD protection cell, having two terminals, one terminal electrically connected to the drain terminal of the power P-type MOS device and the other terminal electrically connected to the ground, used for protecting the power P-type MOS device and the power N-type MOS device while the electrostatic discharge appears.
2. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the signals of default A and default B of the non-overlap circuit can be high level or low level during a period of interval.
3. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the signal of default A of the non-overlap circuit and the EN signal of the digital logic AND gate have the same level during a period of interval.
4. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the power P-type MOS device and the power N-type MOS device are with the different operation state during the same period of interval.
5. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the signals of default B of the non-overlap circuit and the EN signal of the digital logic AND gate have different level while the electrostatic discharge appears.
6. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the voltage applied on the Lx pin is less than the breakdown voltage of the power N-type MOS device.
7. The circuit with ESD protection for a switching regulator as claimed in claim 1 , wherein the circuit has an ESD capability of Human Body Model (HBM) higher than 8 kV.
8. A circuit with ESD protection for a switching regulator, comprising:
a non-overlap circuit, having a first output terminal and a second output terminal, the first output terminal outputting a signal of default A and the second output terminal outputting a signal of default B;
a power P-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the first output terminal of the non-overlap circuit and receiving the signal of default A outputted from the first output terminal of the non-overlap circuit;
a diode, electrically connected to the source terminal and the drain terminal of the power P-type MOS device, used for providing a pathway for an electrostatic discharge;
a digital logic AND gate, having two input terminals and a output terminal, one of the input terminals electrically connected to the second output terminal of the non-overlap circuit and receiving the signal of default B from the second output terminal of the non-overlap circuit, the other one of the input terminals receiving a EN signal, the output terminal providing a output signal of the digital logic AND gate;
a power N-type MOS device, having a gate terminal, a source terminal and a drain terminal, the drain terminal electrically connected to the drain terminal of the power P-type MOS device, the source terminal electrically connected to a ground;
a RC circuit, comprising a resistor and a capacitor, one of the terminals of the resistor electrically connected to the output terminal of the digital logic gate of AND gate, the resistor receiving and transmitting the output signal of the digital logic AND gate to the gate terminal of the power P-type MOS device, one of the terminals of the capacitor electrically connected to another terminal of the resistor and the gate terminal of the power N-type MOS device and another terminal of the capacitor electrically connected to the ground, used for providing a delay time while the electrostatic discharge appears;
an ESD N-type MOS device, having a gate terminal, a source terminal and a drain terminal, the gate terminal electrically connected to the second terminal of the non-overlap circuit, the drain terminal electrically connected to the drain terminal of the power P-type MOS device, the source terminal electrically connected to the ground, used for providing a pathway for the electrostatic discharge;
a Lx pin, electrically connected to the drain terminal of the power P-type MOS device, the drain terminal of the power N-type MOS device and the drain terminals of the ESD N-type MOS device, used for outputting a converted voltage; and
an ESD protection cell, having two terminals, one terminal electrically connected to the drain terminal of the power P-type MOS device and the other terminal electrically connected to the ground, used for protecting the power P-type MOS device and the power N-type MOS device while the electrostatic discharge appears.
9. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the signals of default A and default B of the non-overlap circuit can be high level or low level during a period of interval.
10. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the signal of default A of the non-overlap circuit and the EN signal of the digital logic AND gate have the same level during a period of interval.
11. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the power P-type MOS device and the power N-type MOS device are with the different operation state during the same period of interval.
12. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the signals of default B of the non-overlap circuit and the EN signal of the digital logic AND gate have different level while the electrostatic discharge appears.
13. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the voltage applied on the Lx pin is less than the breakdown voltage of the terminal of the power N-type MOS device.
14. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the circuit has an ESD capability of Human Body Model (HBM) higher than 8 kV.
15. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the ESD N-type MOS device follows the ESD rule layout.
16. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the power N-type MOS device turns on with the delay time resulted from the RC circuit after the ESD N-type MOS device has turned on.
17. The circuit with ESD protection for a switching regulator as claimed in claim 16 , wherein the delay time is in the range of 5 ns to 20 ns.
18. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the ESD N-type MOS device will always turn on to lower the on-resistance of the power N-type MOS device if the power N-type MOS device turns on.
19. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the ESD N-type MOS device is located below the Lx pin.
20. The circuit with ESD protection for a switching regulator as claimed in claim 8 , wherein the power P-type MOS device, the power N-type MOS device and the ESD N-type MOS device can be replaced and selected from Heterojunction Bipolar Transistor (HBT), High Electronic Mobility Transistor (HEMT), Pseudomorphic HEMT (PHEMT), Complementary Metal Oxide Semiconductor Filed Effect Transistor (CMOS) and Laterally Diffused Metal Oxide Semiconductor Filed Effect Transistor (LDMOS).