Charge injection mechanism for analog-to-digital converters
View Patent ↗A low-cost charge injection mechanism may enable oversampling to be used on low frequency signals by injecting dither noise into the ADC input. The dither noise can reduce the quantization noise allowing even direct current (DC) signals to be oversampled correctly. A low-cost charge injection mechanism can also be used to improve the ENOB by characterizing the ADC and digitally correcting the converted signal for non-linearity errors such as INL. Reducing INL errors may also allow a higher degree of oversampling to be used to further improve the ENOB.
1. An integrated circuit device, comprising:
a digital controller;
an analog-to-digital converter (ADC) coupled to the digital controller;
a sample-and-hold circuit coupled to an input of the ADC, the sample-and-hold circuit configurable for sampling an analog signal; and
one or more current sources coupled to the controller and the sample-and-hold circuit, the one or more current sources configurable by the controller to inject a controlled amount of charge into the sample-and-hold circuit or to remove a controlled amount of charge stored by the sample-and-hold circuit.
2. The integrated circuit device of claim 1 , further comprising:
a controllable switch coupled to the analog input signal; and
a central processing unit coupled to the switch and configurable to control the switch to allow the analog signal to be sampled by the sample-and-hold circuit.
3. The integrated circuit device of claim 1 , further comprising:
memory coupled to the processor and an output of the ADC, the memory configurable for storing a digital value resulting from conversion of one or more samples of the analog signal by the ADC.
4. The integrated circuit device of claim 3 , further comprising:
compensation data stored in the memory, the compensation data for correcting errors in the digital values, the compensation data generated based on a characterization of the ADC performed by the integrated circuit device using the one or more current sources.
5. The integrated circuit device of claim 1 , where the one or more current sources further comprise:
a first current source coupled to the digital controller and the sample-and-hold circuit, where the first current source is turned on by the digital controller for a first on-time to allow charge to be injected into the sample-and-hold circuit; and
a second current source coupled to the digital controller and the sample-and-hold circuit, where the second current source is turned on by the digital controller for a second on-time to allow charge to be removed from the sample-and-hold circuit,
where the digital controller turns only one of the first and second current sources on at a time.
6. The integrated circuit device of claim 1 , where the first on-time or the second on-time is calculated to provide one Least Significant Bit (LSB) of charge from the first current source or the second current source, respectively.
7. The integrated circuit device of claim 1 , where the sample-and-hold circuit is included in the ADC.
8. The integrated circuit device of claim 1 , where the one or more current sources inject or remove random amounts of charge.
9. The integrated circuit device of claim 8 , where the random amounts of charge are generated by a Linear Feedback Shift Register (LFSR).
10. A method performed on an integrated circuit device, the method comprising:
sampling an analog input signal using a sample-and-hold circuit;
modifying the sampled analog input signal with a controlled amount of charge generated by one or more current sources controlled by a digital controller; and
converting the modified sampled analog input signal into a digital value using an analog-to-digital converter (ADC).
11. The method of claim 10 , further comprising:
generating compensation data on the integrated circuit device using the one or more current sources and the ADC; and
correcting errors in the digital values using the compensation data.
12. The method of claim 11 , where generating compensation data further comprises:
performing a linear sweep of charge injections in a range of interest;
converting sample voltages with injected charges to digital values; and
calculating compensation data based on digital values.
13. The method of claim 10 , where modifying the sampled analog input signal with a controlled amount of charge generated by one or more current sources controlled by a digital controller, further comprises:
calculating on-time; and
turning on the one or more current sources for a time period substantially equal to the on-time.
14. The method of claim 13 , where calculating on-time further comprises:
sampling a random value;
using the one or more current sources to adding a small amount of charge repeatedly to the random value until the ADC changes code one or more times; and
setting the on-time to accumulated on-times for the one or more current sources during the calculating of on-time.
15. A system comprising:
means for sampling an analog input signal using a sample-and-hold circuit;
means for modifying the sampled analog input signal with a controlled amount of charge generated by one or more current sources controlled by a digital controller; and
means for converting the modified sampled analog input signal into a digital value using an analog-to-digital converter (ADC).