IP Library Granted Patent US 8,466,544
Granted Patent B2
US 8,466,544 · App. 13/035,669 · Granted Jun 18, 2013

Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP

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Quick Facts
Patent No.
US 8,466,544
App. No.
13/035,669
Granted
Jun 18, 2013
Kind
B2
Abstract

A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Claims (65)

1. A method of making a semiconductor device, comprising:

providing a substrate including a plurality of first conductive vias formed through the substrate and a first conductive layer formed over the substrate;

providing a carrier;

mounting a semiconductor die over the carrier;

mounting the substrate to the semiconductor die opposite the carrier;

depositing an encapsulant between the substrate and carrier around the semiconductor die;

forming a plurality of second conductive vias through the substrate and encapsulant, the second conductive vias being electrically connected to the first conductive layer and first conductive vias;

removing the carrier to expose a surface of the second conductive vias; and

forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate, the interconnect structure being electrically connected to the second conductive vias.

2. The method of claim 1 , wherein the second conductive vias protrude from the encapsulant.

3. The method of claim 1 , further including providing a plurality of alignment marks over the carrier to aid with mounting the semiconductor die.

4. The method of claim 1 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the substrate, second conductive vias, and interconnect structure.

5. The method of claim 1 , further including stacking a plurality of semiconductor dies between the substrate and interconnect structure.

6. The method of claim 1 , wherein forming the interconnect structure includes:

forming a second conductive layer over the surface of the encapsulant and semiconductor die opposite the substrate; and

forming an insulating layer around the second conductive layer.

7. A method of making a semiconductor device, comprising:

providing a substrate having a conductive path through the substrate;

providing a semiconductor die;

mounting the substrate to the semiconductor die;

depositing an encapsulant around the semiconductor die;

forming a plurality of conductive vias through the substrate and encapsulant, the conductive vias being electrically connected to the conductive path through the substrate; and

forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate, the interconnect structure being electrically connected to the conductive vias, wherein forming the interconnect structure includes,

forming a conductive layer over the surface of the encapsulant and semiconductor die opposite the substrate, and

forming an insulating layer around the conductive layer.

8. The method of claim 7 , wherein the conductive vias protrude from the encapsulant.

9. The method of claim 7 , further including aligning the interconnect structure to the conductive vias.

10. The method of claim 7 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the substrate, conductive vias, and interconnect structure.

11. The method of claim 7 , further including stacking a plurality of semiconductor dies between the substrate and interconnect structure.

12. The method of claim 7 , further including depositing the encapsulant around the semiconductor die through an opening in the substrate.

13. A method of making a semiconductor device, comprising:

providing a semiconductor die;

mounting a substrate to the semiconductor die;

depositing an encapsulant around the semiconductor die through an opening in the substrate;

forming a plurality of conductive vias through the substrate and encapsulant; and

forming an interconnect structure over a surface of the encapsulant and semiconductor die opposite the substrate, the interconnect structure being electrically connected to the conductive vias.

14. The method of claim 13 , wherein the conductive vias protrude from the encapsulant.

15. The method of claim 13 , further including aligning the interconnect structure to the conductive vias.

16. The method of claim 13 , further including removing a portion of the semiconductor die prior to mounting the substrate.

17. The method of claim 13 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the substrate, conductive vias, and interconnect structure.

18. The method of claim 13 , further including stacking a plurality of semiconductor dies between the substrate and interconnect structure.

19. A method of making a semiconductor device, comprising:

providing a first semiconductor die including an active surface and a back surface opposite the active surface;

mounting a substrate over the back surface of the first semiconductor die;

disposing an encapsulant around the first semiconductor die;

forming a first interconnect structure through the substrate and encapsulant;

forming a conductive layer over the encapsulant and active surface of the first semiconductor die; and

removing a portion of the first semiconductor die after disposing the encapsulant.

20. The method of claim 19 , further including:

stacking a plurality of semiconductor devices; and

electrically connecting the semiconductor devices through the substrate, first interconnect structure, and conductive layer.

21. The method of claim 19 , further including:

disposing a second semiconductor die between the first semiconductor die and the substrate; and

forming a second interconnect structure between the substrate and second semiconductor die.

22. The method of claim 19 , further including:

providing one or more alignment marks;

mounting the substrate aligned to the alignment marks; and

disposing the encapsulant around the alignment marks.

23. The method of claim 19 , further including forming the conductive layer aligned to the first interconnect structure.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0235. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065236/0741 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0235 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2011
From: PAGAILA, REZA A.
To: STATS CHIPPAC, LTD.
Reel/Frame 025867/0639 →