Stacking package structure with chip embedded inside and die having through silicon via and method of the same
The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.
1. A method of forming a semiconductor die assembly, comprising:
aligning an inter-connecting bonding pad and a through silicon via of a silicon wafer which includes a first die to a through hole passing through a panel substrate which includes a second die embedded therein, thereby bonding said panel substrate facing to the backside of said silicon wafer, wherein said through silicon via is formed to connect said inter-connecting bonding pad;
curing an adhesion dielectric layer that is formed on said panel substrate;
sputtering a seed metal layer from the back side of said panel substrate;
coating a photo resist from the back side of said panel substrate and opening said through hole area;
filling a metal material into said through hole area to couple to said inter-connecting bonding pad of said first die and said through silicon via, and to couple to final terminal pads of said panel substrate; and
stripping said photo resist and etching said seed metal layer.
2. The method of claim 1 , further comprising a step of forming solder balls on under bump metallurgy (UBM) of said panel substrate after stripping said photo resist.
3. The method of claim 1 , wherein the material of said panel substrate includes FR4, FR5, BT, PI and epoxy resin.
4. The method of claim 1 , wherein said metal material includes Cu, Cu/Ni or Sn/Ag/Cu.