IP Library Granted Patent US 9,252,172
Granted Patent B2
US 9,252,172 · App. 13/149,628 · Granted Feb 2, 2016

Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region

Inventors: Seng Guan Chow (Singapore, SG); Lee Sun Lim (Singapore, SG); Rui Huang (Singapore, SG); Xusheng Bao (Singapore, SG); Ma Phoo Pwint Hlaing (Singapore, SG)
Assignee: STATS ChipPAC, Ltd.
H01L27/14618H01L2224/73265H01L2924/01322H01L2924/13091H01L2924/1461
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Quick Facts
Patent No.
US 9,252,172
App. No.
13/149,628
Granted
Feb 2, 2016
Kind
B2
Abstract

A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Claims (35)

1. A semiconductor device, comprising:

a substrate including a transparent optical material capable of passing light;

a plurality of spacers mounted to the substrate;

a first semiconductor die disposed over the spacers including an active region of the first semiconductor die capable of receiving light and a plurality of conductive vias formed through the first semiconductor die, the active region oriented toward the substrate with a gap through the spacers over the active region between the substrate and first semiconductor die;

an encapsulant deposited over the first semiconductor die and substrate; and

an interconnect structure formed over the encapsulant and first semiconductor die with the interconnect structure electrically connected to the conductive vias.

2. The semiconductor device of claim 1 , wherein the active region is separated from the substrate by the plurality of spacers.

3. The semiconductor device of claim 2 , wherein the first semiconductor die is disposed over the plurality of spacers so as to form a seal and prevent the encapsulant from contacting the active region or substrate.

4. The semiconductor device of claim 1 , wherein the active region includes a sensor or micro-electro mechanical system responsive to light received through the substrate.

5. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die.

6. A semiconductor device, comprising:

a substrate including an optical material capable of passing light;

a spacer mounted to a surface of the substrate;

a first semiconductor die including a plurality of conductive vias formed through the first semiconductor die disposed over the spacer with the first semiconductor die responsive to the light through an opening in the spacer; and

an interconnect structure formed over the first semiconductor die and electrically connected through the conductive vias to the first semiconductor die.

7. The semiconductor device of claim 6 , further including an encapsulant deposited over the first semiconductor die and the substrate.

8. The semiconductor device of claim 6 , wherein an active region of the first semiconductor die is oriented toward the substrate and positioned over the opening in the spacer.

9. The semiconductor device of claim 6 , wherein an active region of the first semiconductor die includes a sensor or micro-electronic mechanical system.

10. The semiconductor device of claim 6 , further including a second semiconductor die disposed over the first semiconductor die.

11. A semiconductor device, comprising:

a substrate including a region capable of passing an external stimuli;

a spacer disposed over a surface of the substrate;

a first semiconductor die disposed over the spacer and substrate and responsive to the external stimuli through an opening in the spacer;

a conductive via formed through the first semiconductor die; and

an interconnect structure formed over the first semiconductor die and coupled to the conductive via.

12. The semiconductor device of claim 11 , further including an encapsulant deposited over the first semiconductor die and the substrate.

13. The semiconductor device of claim 11 , wherein an active region of the first semiconductor die includes a sensor or micro-electronic mechanical system responsive to the external stimuli received through the region of the substrate capable of passing the external stimuli.

14. The semiconductor device of claim 11 , further including a second semiconductor die disposed over the first semiconductor die.

15. The semiconductor device of claim 11 , wherein the external stimuli includes light.

16. A semiconductor device, comprising:

a substrate including a region capable of passing an external stimuli;

a semiconductor die disposed over the substrate including a conductive via formed through the semiconductor die; and

a spacer disposed between the substrate and the semiconductor die with an active region of the semiconductor die oriented toward the substrate and positioned over an opening in the spacer.

17. The semiconductor device of claim 16 , wherein the active region of the semiconductor die includes a sensor or micro-electronic mechanical system responsive to the external stimuli received through the region of the substrate capable of passing the external stimuli.

18. The semiconductor device of claim 16 , wherein the external stimuli includes light.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON COVERSHEET FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED ON REEL 038378 FRAME 0418. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Sep 5, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064908/0920 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0418 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2011
From: CHOW, SENG GUAN; HUANG, RUI; LIM, LEE SUN; BAO, XUSHENG; HLAING, MA PHOO PWINT
To: STATS CHIPPAC, LTD.
Reel/Frame 026365/0082 →
Continuity (1)
Related Publication 20120306038A1 · Dec 6, 2012