Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via

1. A method of forming a via structure, the method comprising the steps of:

forming a through-silicon via in a substrate, wherein the substrate has a first-surface and a second-surface;

forming a back-end-of-line (BEOL) wiring level on the first-surface of the substrate, wherein the BEOL wiring level includes a contact pad;

forming a photosensitive polyimide layer on the BEOL wiring level;

forming an opening in the photosensitive polyimide layer;

forming a ball limiting metallization (BLM) layer on the opening in the photosensitive polyimide layer;

forming an adhesive layer on the photosensitive polyimide layer and the BLM layer;

forming a mechanical support carrier layer on the adhesive layer;

forming an electrical path through the mechanical support carrier layer, wherein the electrical path includes the contact pad; and

performing an electroplating technique to fill the through-silicon via with a plated-conductive material.

2. The method of claim 1 , wherein forming the through-silicon via comprises:

forming an opening in the substrate utilizing an etching/removal technique that includes RIE or wet etching;

depositing an optional dielectric layer directly adjacent to sidewalls of the opening in the substrate utilizing a chemical vapor deposition technique;

depositing a diffusion barrier layer directly adjacent to the optional dielectric layer, or directly adjacent to the sidewalls of the opening in the substrate;

depositing a sacrificial layer directly adjacent to the diffusion barrier layer and proximate to the contact pad;

recessing the second-surface of the substrate to form a third-surface of the substrate;

depositing a dielectric layer proximate to the third-surface of the substrate; and

removing the sacrificial layer selective to the contact pad prior to performing the electroplating technique.

3. The method of claim 2 , wherein the diffusion barrier layer comprises tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), titanium (Ti), or titanium nitride (TiN) deposited utilizing a technique that includes CVD, physical vapor deposition (PVD), or atomic layer deposition (ALD).

4. The method of claim 2 , wherein the sacrificial layer comprises poly-silicon, polyimide, or an oxide that is deposited utilizing CVD, physical vapor deposition (PVD), or spin-on approaches.

5. The method of claim 1 , wherein forming the BEOL wiring level comprises:

forming the contact pad on the through-silicon via; and

forming a metallization layer that includes the contact pad.

6. The method of claim 5 , wherein forming the BLM layer comprises:

connecting the BLM layer to the metallization layer through the opening in the photosensitive polyimide layer; or

connecting the BLM layer to the metallization layer through the opening in the photosensitive polyimide layer, wherein a collapse chip connection (C4) is formed on the BLM layer and is present during the electroplating technique.

7. The method of claim 1 , wherein the forming the through-silicon via is performed before FEOL processing, during FEOL processing, after FEOL processing but before BEOL processing, during BEOL processing, after BEOL processing, or after mechanical support carrier-attach and backside thinning.

8. The method of claim 1 , wherein forming the mechanical support carrier layer comprises creating an opening in the mechanical support carrier layer that exposes a portion of the adhesive layer.

9. The method of claim 8 , wherein performing the electroplating technique to fill the through-silicon via comprises applying a voltage to the adhesive layer through the opening in the mechanical support carrier layer, which causes current to flow to the contact pad and the plated-conductive material from an electroplating solution to fill the through-silicon via.