IP Library Granted Patent US 8,409,923
Granted Patent B2
US 8,409,923 · App. 13/161,368 · Granted Apr 2, 2013

Integrated circuit packaging system with underfill and method of manufacture thereof

Inventors: Oh Han Kim (Ichon-si, KR); Yong Hee Kang (Ansan-si, KR); DaeSik Choi (Seoul, KR)
Assignee: STATS Chippac Ltd.
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Quick Facts
Patent No.
US 8,409,923
App. No.
13/161,368
Granted
Apr 2, 2013
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a projection formed along a perimeter of a first surface of the substrate; mounting an integrated circuit over the first surface; forming a protruding interconnect over the first surface between the projection and the integrated circuit; and forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection.

Claims (50)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate with a projection formed along a perimeter of a first surface of the substrate;

mounting an integrated circuit over the first surface;

forming a protruding interconnect over the first surface between the projection and the integrated circuit; and

forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection.

2. The method as claimed in claim 1 wherein:

providing the substrate with the projection includes providing a projection sidewall substantially coplanar with a substrate sidewall.

3. The method as claimed in claim 1 wherein:

providing the integrated circuit includes providing a flip-chip.

4. The method as claimed in claim 1 further comprising:

exposing a substantially equal portion of each of the protruding interconnect from the underfill.

5. The method as claimed in claim 1 wherein:

forming the underfill includes exposing the integrated circuit from the underfill.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate with a projection formed along a perimeter of a first surface of the substrate;

mounting an integrated circuit over the first surface;

forming a protruding interconnect over the first surface between the projection and the integrated circuit;

forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection; and

attaching a device over the integrated circuit by electrically connecting an external connection of the device to the protruding interconnect.

7. The method as claimed in claim 6 wherein:

providing the substrate with the projection includes forming the projection as a continuous structure.

8. The method as claimed in claim 6 wherein:

providing the substrate with the projection includes forming the projection integral with the substrate.

9. The method as claimed in claim 6 wherein:

attaching the device includes attaching an integrated circuit package.

10. The method as claimed in claim 6 wherein:

attaching the device includes forming a package-on-package structure.

11. An integrated circuit packaging system comprising:

a substrate with a projection along a perimeter of a first surface of the substrate;

an integrated circuit over the first surface of the substrate and attached thereto;

a protruding interconnect over the first surface between the projection and the integrated circuit; and

an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection.

12. The system as claimed in claim 11 further comprising:

a projection sidewall substantially coplanar with a substrate sidewall.

13. The system as claimed in claim 11 wherein:

the integrated circuit includes a flip-chip.

14. The system as claimed in claim 11 wherein:

the underfill exposes a substantially equal portion of each of the protruding interconnect.

15. The system as claimed in claim 11 wherein:

the integrated circuit is exposed from the underfill.

16. The system as claimed in claim 11 further comprising:

a device over the integrated circuit, the device including an external connection electrically connected to the protruding interconnect.

17. The system as claimed in claim 16 wherein:

the projection includes a continuous structure.

18. The system as claimed in claim 16 wherein:

the projection is integral with the substrate.

19. The system as claimed in claim 16 wherein:

the device includes an integrated circuit package.

20. The system as claimed in claim 16 wherein:

a width of the projection is less than the height of the projection.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME ON THE COVER SHEET FROM STATS CHIPPAC PTE. LTE. TO STATS CHIPPAC PTE. LTD. PREVIOUSLY RECORDED ON REEL 038378 FRAME 0244. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 31, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 065239/0786 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0244 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2011
From: KIM, OH HAN; KANG, YONG HEE; CHOI, DAESIK
To: STATS CHIPPAC LTD.
Reel/Frame 026523/0825 →
Continuity (1)
Related Publication 20120319300A1 · Dec 20, 2012