Method and system for a GAN vertical JFET utilizing a regrown gate
View Patent ↗A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
1. A method of fabricating an epitaxial transistor, the method comprising:
providing a III-nitride substrate;
forming a drift region at least partly by epitaxially growing a first III-nitride epitaxial layer of a first conductivity type from the III-nitride substrate, wherein the first III-nitride epitaxial layer has a first dopant concentration;
forming a channel region at least partly by epitaxially growing a second III-nitride epitaxial layer of the first conductivity type from the drift region, wherein the second III-nitride epitaxial layer has a second dopant concentration;
forming a source region at least partly by epitaxially growing a third III-nitride epitaxial layer of the first conductivity type from the channel region, wherein the third III-nitride epitaxial layer has a third dopant concentration greater than the first dopant concentration; and
after forming the channel region, simultaneously protecting the source region and forming a gate region at least partly by epitaxially growing a fourth III-nitride epitaxial layer from both the preexisting drift and channel regions, and wherein the source region is protected such that the fourth III-nitride epitaxial layer does not grow from the source region while the fourth III-nitride epitaxial layer is grown from both the preexisting drift and channel regions, and wherein the gate region has a second conductivity type.
2. The method of claim 1 further comprising removing at least a portion of the third III-nitride epitaxial layer and at least a portion of the second III-nitride epitaxial layer to form a GaN channel region of the second III-nitride epitaxial layer.
3. The method of claim 2 further comprising forming a fourth III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer.
4. The method of claim 3 further comprising:
forming a first metallic structure electrically coupled to the III-nitride substrate; and
forming a second metallic structure electrically coupled to the fourth III-nitride epitaxial layer.
5. The method of claim 3 wherein the first conductivity type is n type and the second conductivity type is p type.
6. The method of claim 1 wherein at least one of the first dopant concentration, the second dopant concentration, or the third dopant concentration is non-uniform.
7. The method of claim 1 wherein a thickness of the first III-nitride epitaxial layer is between 1 μm and 100 μm.