Three-dimensional dynamic random access memory with an ancillary electrode structure
A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.
1. A three-dimensional dynamic random access memory with an ancillary electrode structure, comprising:
a substrate;
at least one bit line which is formed on the substrate by doping and diffusing a doping element and includes a growth zone and a separation zone;
at least one pillar element which is formed on the growth zone of the bit line and includes a top wall remote from the bit line and a side wall between the bit line and the top wall, the side wall being perpendicular to the bit line, the top wall including an opening;
a first dielectric layer formed on the separation zone of the bit line and a surface of the pillar element;
at least one ancillary electrode formed on a surface of the first dielectric layer corresponding to the separation zone and adjacent to the pillar element;
a second dielectric layer connecting to the first dielectric layer and encasing the ancillary electrode;
at least one character line formed on the surface of the first dielectric layer remote from the side wall and parallel with a surface of the substrate and perpendicular to the bit line, and spaced from the ancillary electrode via the second dielectric layer; and
at least one capacitor formed on the top wall of the pillar element and connected to the pillar element through the opening.
2. The three-dimensional dynamic random access memory of claim 1 , wherein the first dielectric layer and the second dielectric layer are made of different materials.
3. The three-dimensional dynamic random access memory of claim 1 , wherein the growth zone and the separation zone respectively include multiple sets spaced from each other, the pillar element including multiple sets corresponding to the growth zone.
4. The three-dimensional dynamic random access memory of claim 3 , wherein the character line includes a first character line and a second character line that are located respectively on one side of neighboring side walls of the pillar elements without contacting with each other.
5. The three-dimensional dynamic random access memory of claim 3 , wherein the bit line includes multiple sets parallel with and spaced from each other.
6. The three-dimensional dynamic random access memory of claim 5 , wherein the ancillary electrode is located between the pillar elements and parallel with the surface of the substrate and perpendicular to the bit line.
7. The three-dimensional dynamic random access memory of claim 1 , wherein the doping element is a 3A or 5A group element so that the bit line becomes a P-type or N-type semiconductor.
8. The three-dimensional dynamic random access memory of claim 1 , wherein the bit line is formed by doping and diffusing the doping element in the substrate through an ion implantation technique, a furnace doping and diffusion technique or a plasma diffusion technique.