Multi-phase voltage controlled oscillator using capacitance degenerated single ended transconductance stage and inductance/capacitance load
View Patent ↗An electrical circuit includes a first transistor having a first source, a first drain, and a first gate, whereby the first transistor receives an input voltage through the first gate. An output voltage terminal outputs voltage from the first transistor and is connected to the first drain. A second transistor includes a second source, a second drain, and a second gate, whereby the second transistor receives a bias voltage through the second gate, and wherein the first source is connected to the second drain. A first capacitor is connected to the first source, the second source, and the second drain. An inductor is connected to the first drain. A second capacitor is connected in parallel with the inductor and further connected to the first drain.
1. A multi-phase voltage controlled oscillator (VCO) comprising:
a chain of at least four ring oscillator delay stage cells, wherein each stage comprises a Gm/C delay element and a LC tank load that creates no ambiguity of phase rotation direction, wherein an output voltage of each stage in said chain is input as an input voltage of a subsequent stage in said chain, wherein the output voltage of a last stage in said chain is fed back as an input voltage of a first stage in said chain, wherein each delay stage in said chain exhibits no phase shift from input to output at resonance, and wherein each stage in said chain comprises:
a pair of transistors comprising a first transistor connected to a second transistor without an intervening switch therebetween;
said first transistor comprising a first source, a first drain, a first bulk terminal, and a first gate, said first transistor receiving an input voltage through said first gate;
an output voltage terminal that outputs voltage from said first transistor and is connected to said first drain;
said second transistor comprising a second source, a second drain, a second bulk terminal, and a second gate, said second transistor receiving a bias voltage through said second gate, wherein said first source is connected to said second drain without an intervening switch therebetween;
a first capacitor connected to said first source, said second source, and said second drain;
an inductor connected to said first drain; and
a second capacitor connected in parallel with said inductor to form said LC tank load,
wherein said LC tank load is directly connected to said first drain without direct connection to said first gate and without direct connection to any other transistor other than said first transistor,
wherein said first bulk terminal is connected to said first source and said second bulk terminal is connected to ground, and
wherein said first transistor and said second transistor are connected to each other in a non-cross-coupled configuration.
2. The multi-phase VCO of claim 1 , wherein the first and second transistors comprise any of a n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor.
3. The multi-phase VCO of claim 1 , further comprising a power supply voltage terminal connected to any of said inductor and said second source.
4. The multi-phase VCO of claim 1 , wherein a top plate of said first capacitor is connected to said first source and said second drain, and wherein a bottom plate of said first capacitor is connected to ground.
5. The multi-phase VCO of claim 1 , wherein said second transistor transfers said input voltage into current and creates a phase shift delay in the output voltage.
6. The multi-phase VCO of claim 1 , wherein said chain of at least four ring oscillator delay stage cells generates 0, 90, 180, and 270 degree phases when said chain comprises four ring oscillator delay stage cells.
7. The multi-phase VCO of claim 1 , wherein chain of at least four ring oscillator delay stage cells generates 0, 45, 90, 135, 180, 225, 270, and 315 degree phases when said chain comprises eight ring oscillator delay stage cells.
8. The multi-phase VCO of claim 1 , wherein said first capacitor degenerates an input transconductance of said first transistor.
9. The multi-phase VCO of claim 1 , wherein an input/output transfer function of each said unit delay stage comprises:
V
OUT
V
IN
=
-
G
ds
_
tail
G
T
1
+
s
z
1
1
+
s
p
1
,
z
1
≈
G
ds
_
tail
C
deg
,
p
1
≈
k
G
m
_
in
(
C
gs
_
in
+
C
deg
)
,
k
=
G
T
G
T
+
G
ds
_
in
,
wherein G ds — tail comprises a channel admittance of said second transistor, wherein G T comprises an admittance of said inductor in parallel with said second capacitor, wherein C deg comprises a degenerative capacitance, wherein G m — in comprises a transconductance of said first transistor, and wherein G ds — in comprises a channel admittance of said first transistor.
10. The multi-phase VCO of claim 9 , wherein said first capacitor degenerates said transconductance of said first transistor and introduces a zero into said input/output transfer function, wherein said zero comprises
G
ds
_
tail
C
deg
and provides a 90 degrees phase lead when frequency is below
k
G
m
_
in
(
C
gs
_
in
+
C
deg
)
.
11. A multi-phase voltage controlled oscillator (VCO) comprising:
a chain of a plurality of ring oscillator delay stage cells, wherein each stage comprises a Gm/C delay element and a LC tank load that creates no ambiguity of phase rotation direction, wherein an output voltage of each stage in said chain is input as an input voltage of a subsequent stage in said chain, wherein the output voltage of a last stage in said chain is fed back as an input voltage of a first stage in said chain, wherein each delay stage in said chain exhibits no phase shift from input to output at resonance, and wherein each stage in said chain comprises:
a pair of transistors comprising an input transistor connected to a bias transistor without an intervening switch therebetween;
said input transistor comprising a first source terminal, a first drain terminal, a first bulk terminal, and a first gate terminal, said input transistor adapted to receive an input voltage through said first gate terminal;
an output voltage terminal adapted to output voltage from said input transistor, said output voltage terminal being connected to said first drain terminal;
said bias transistor comprising a second source terminal, a second drain terminal, a second bulk terminal, and a second gate terminal, wherein said bias transistor is adapted to receive a bias voltage through said second gate terminal, and wherein said first source terminal is connected to said second drain terminal without an intervening switch therebetween;
a degenerative capacitor connected to said first source terminal, said second source terminal, and said second drain terminal, wherein said degenerative capacitor degenerates an input transconductance of said input transistor; and
said LC tank load directly connected to said first drain terminal without direct connection to said first gate terminal and without direct connection to any other transistor other than said input transistor, wherein said LC tank load comprises:
a tank inductor connected to said first drain terminal; and
a tank capacitor connected in parallel with said tank inductor and further connected to said first drain terminal,
wherein said first bulk terminal is connected to said first source and said second bulk terminal is connected to ground, and
wherein said input transistor and said bias transistor are connected to each other in a non-cross-coupled configuration.
12. The multi-phase VCO of claim 11 , wherein the input and bias transistors comprise any of a n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor.
13. The multi-phase VCO of claim 11 , further comprising a power supply voltage terminal that receives a power supply voltage and is connected to any of said tank inductor and said second source terminal.
14. The multi-phase VCO of claim 11 , wherein a top plate of said degenerative capacitor is connected to said first source terminal and said second drain terminal, and wherein a bottom plate of said degenerative capacitor is connected to ground.
15. The multi-phase VCO of claim 11 , wherein said bias transistor transfers said input voltage into current and creates a phase shift delay in the output voltage.
16. The multi-phase VCO of claim 11 , wherein said chain of at least four ring oscillator delay stage cells generates 0, 90, 180, and 270 degree phases when said chain comprises four ring oscillator delay stage cells.
17. The multi-phase VCO of claim 11 , wherein said chain of at least four ring oscillator delay stage cells generates 0, 45, 90, 135, 180, 225, 270, and 315 degree phases when said chain comprises eight ring oscillator delay stage cells.
18. The multi-phase VCO of claim 11 , wherein an input/output transfer function of each said unit delay stage comprises:
V
OUT
V
IN
=
-
G
ds
_
tail
G
T
1
+
s
z
1
1
+
s
p
1
,
z
1
≈
G
ds
_
tail
C
deg
,
p
1
≈
k
G
m
_
in
(
C
gs
_
in
+
C
deg
)
,
k
=
G
T
G
T
+
G
ds
_
in
,
wherein G ds — tail comprises a channel admittance of said bias transistor, wherein G T comprises an admittance of said tank inductor in parallel with said tank capacitor, wherein C deg comprises a degenerative capacitance, wherein G m — in comprises a transconductance of said input transistor, and wherein G ds — in comprises a channel admittance of said input transistor.
19. The multi-phase VCO of claim 18 , wherein said degenerative capacitor degenerates said transconductance of said input transistor and introduces a zero into said input/output transfer function, wherein said zero comprises
G
ds
_
tail
C
deg
and provides a 90 degrees phase lead when frequency is below
k
G
m
_
in
(
C
gs
_
in
+
C
deg
)
.